Added docs

controller.vhd

@@ -1,283 +1,268 @@
 ----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer: 
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
--- 
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    18:47:36 05/23/2016 
--- Design Name: 
--- Module Name:    controller - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 use IEEE.NUMERIC_STD.ALL;
 
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity controller is
-    Port ( clk : in  STD_LOGIC;
+    Generic (freq_res: natural:=17);                 -- width of frequency input (log2(max_freq))
-			  rst: in STD_LOGIC;
+    Port ( clk : in  STD_LOGIC;                      -- Clock Input
-           enc_right : in  STD_LOGIC;
+           rst: in STD_LOGIC;                        -- High active, async reset
-           enc_ce : in  STD_LOGIC;
+           enc_right : in  STD_LOGIC;                -- Encoder Input: 1= Direction Right, 0 = Direction Left
-			  enc_btn: in STD_LOGIC;
+           enc_ce : in  STD_LOGIC;                   -- Encoder Input: Clock Enable for Signal above
-			  form : in unsigned(1 downto 0);
+           enc_btn: in STD_LOGIC;                    -- Encoder Input: Debounced Button (High active)
-			  lcd_busy: in STD_LOGIC;
+           form : in unsigned(1 downto 0);           -- Form selection (mapping see dds.vhd)
-			  lcd_data: out unsigned(7 downto 0);
+           lcd_busy: in STD_LOGIC;                   -- LCD Feedback: Busy Signal: 1= LCD is currently busy
-			  lcd_newchar: out STD_LOGIC;
+           lcd_data: out unsigned(7 downto 0);       -- LCD Output: Data output
-			  lcd_newpos : out STD_LOGIC;
+           lcd_newchar: out STD_LOGIC;               -- LCD Output: Send a new character to the lcd
-           freq_out : out  unsigned (16 downto 0));
+           lcd_newpos : out STD_LOGIC;               -- LCD Output: Send a new position/adress to the lcd
+           freq_out : out  unsigned (freq_res-1 downto 0));  -- Frequency Output (Treshould in Hz)
 end controller;
 
 architecture Behavioral of controller is
-	type states is(S_WAIT, 
+   -- FSM with the following states:
-						S_FORM_PREF, 	-- prints the form prefix ("Form:")
+   type states is(S_WAIT,         -- wait till the lcd is no longer busy, and returns in a specific state afterwards
-						S_FREQ_PREF,  	-- frequenz prefix ("Freq: 00000 Hz")
+                  S_FORM_PREF,    -- prints the form prefix ("Form:")
-						S_FORM_CONT, 	-- form content ("Rechteck, Sinus...")
+                  S_FREQ_PREF,    -- frequenz prefix ("Freq: 00000 Hz")
-						S_FREQ_CONT,  -- frequenz content ("-----")
+                  S_FORM_CONT,    -- form content ("Rechteck, Sinus...")
-						S_IDLE );
+                  S_FREQ_CONT,    -- frequenz content ("-----")
-						
+                  S_IDLE );       -- controller is idle and waits on user input
-	signal state_reg, state_next : states := S_WAIT;
+                  
-	signal ret_state_reg, ret_state_next: states := S_FORM_PREF; 
+   signal state_reg, state_next : states := S_WAIT;              -- Current State
+   signal ret_state_reg, ret_state_next: states := S_FORM_PREF;  -- State to return to, after S_WAIT 
 
    ----- Edge detection registers -----
-	signal btn_old_reg, btn_old_next : std_logic := '0';
+   signal btn_old_reg, btn_old_next : std_logic := '0';
-	signal enc_old_reg, enc_old_next: std_logic :='0';
+   signal enc_old_reg, enc_old_next: std_logic :='0';
-	signal busy_old_reg, busy_old_next : std_logic := '0';
+   signal form_old_reg, form_old_next : unsigned (1 downto 0) := (others => '0');
-	signal form_old_reg, form_old_next : unsigned (1 downto 0) := (others => '0');
+   
-	
+   
-	--digitnr which is currently edited 0-4
+   signal digpos_reg, digpos_next : unsigned(2 downto 0)  := (others => '0');  -- digitnr which is currently edited 0-4
-	signal digpos_reg, digpos_next : unsigned(2 downto 0)  := (others => '0');
+   signal charcnt_reg, charcnt_next : unsigned(3 downto 0) := (others => '0'); -- character number which is currently being written out
-	signal charcnt_reg, charcnt_next : unsigned(3 downto 0) := (others => '0');
+   
-	
+   -- Decimal value (0-9) of the sigle frequency digits (array 5x 4bit)
-	-- array 5x 4bit(0-9)
+   type storage_digit is array (0 to 7) of unsigned (3 downto 0);
-	type storage_digit is array (0 to 7) of unsigned (3 downto 0);
+   signal digit_reg, digit_next : storage_digit := (others => (others => '0'));
-	signal digit_reg, digit_next : storage_digit := (others => (others => '0'));
 
-	signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0';
+   signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0';                     -- Register for the LCD Newchar signal
-	signal lcd_newpos_reg,lcd_newpos_next : std_logic := '0';
+   signal lcd_newpos_reg,lcd_newpos_next : std_logic := '0';                       -- Register for the LCD Newpos signal
-	signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0');
+   signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0');     -- Register for the LCD Databus signal
-	
+   
-	signal freq_out_reg, freq_out_next : unsigned (16 downto 0) := (others => '0');
+   signal freq_out_reg, freq_out_next : unsigned (16 downto 0) := (others => '0'); -- Register for the frequency output (in hz)
-	
+   
-	----------------Constants---------------------------------
+   ----------------Constants---------------------------------
-	
+  
-	type character_array_short is array (0 to 7) of character;
+   -- Signal Form Prefix:
-	constant str_form_pref : character_array_short := ( 'F', 'o', 'r','m',':', others => ' ' );
+   type character_array_short is array (0 to 7) of character;
-	
+   constant str_form_pref : character_array_short := ( 'F', 'o', 'r','m',':', others => ' ' );
-	type character_array_long is array (0 to 15) of character;
+   
-	constant str_freq_pref : character_array_long := ( 'F', 'r', 'e','q',':',' ','0','0','0','0','0',' ','H','z', others => ' ' );
+   -- Signal Frequency Prefix/Postfix:
-	
+   type character_array_long is array (0 to 15) of character;
-	type character_form_array is array (0 to 3, 0 to 7) of character;
+   constant str_freq_pref : character_array_long := ( 'F', 'r', 'e','q',':',' ','0','0','0','0','0',' ','H','z', others => ' ' );
-	constant str_form : character_form_array := (
+   
-		 ('S','q','u','a','r','e',' ',' '),
+   -- Signal Form names:
-		 ('S','a','w','t','o','o','t','h'),
+   type character_form_array is array (0 to 3, 0 to 7) of character;
-		 ('T','r','i','a','n','g','l','e'),
+   constant str_form : character_form_array := (
-		 ('S','i','n','e',' ',' ',' ',' ')
+       ('S','q','u','a','r','e',' ',' '),
-		);
+       ('S','a','w','t','o','o','t','h'),
-		
+       ('T','r','i','a','n','g','l','e'),
+       ('S','i','n','e',' ',' ',' ',' ')
+      );
+      
+   -- Possible improvement: Write a helper function which initializes those character arrays from a string
 
 begin
 
-	proc1: process(clk,rst) 
+   -- State register process (sequential)
-	begin
+   proc1: process(clk,rst) 
-		if(rst='1') then
+   begin
-			digpos_reg <= (others => '0');
+      if(rst='1') then
-			digit_reg <=  (others => (others => '0'));
+         digpos_reg <= (others => '0');
-			
+         digit_reg <=  (others => (others => '0'));
-			btn_old_reg <= '0';
+         
-			enc_old_reg <='0';
+         btn_old_reg <= '0';
-			busy_old_reg <= '0';
+         enc_old_reg <='0';
-			form_old_reg <= "00";
+         form_old_reg <= "00";
-			
+         
-			charcnt_reg <= (others => '0');
+         charcnt_reg <= (others => '0');
-			lcd_newchar_reg <= '0';
+         lcd_newchar_reg <= '0';
-			lcd_newpos_reg <= '0';
+         lcd_newpos_reg <= '0';
-			lcd_data_reg <= (others => '0');
+         lcd_data_reg <= (others => '0');
 
-			freq_out_reg <=(others => '0');
+         freq_out_reg <=(others => '0');
-			
+         
-			state_reg <= S_WAIT;
+         -- On reset: wait on display startup and then start with S_FORM_PREF state
-			ret_state_reg <= S_FORM_PREF;
+         state_reg <= S_WAIT;
-			
+         ret_state_reg <= S_FORM_PREF;
-		elsif(rising_edge(clk)) then
+         
-			digpos_reg <= digpos_next;
+      elsif(rising_edge(clk)) then
-			digit_reg <= digit_next;
+         digpos_reg <= digpos_next;
-			
+         digit_reg <= digit_next;
-			btn_old_reg <= btn_old_next;
+         
-			enc_old_reg <= enc_old_next;
+         btn_old_reg <= btn_old_next;
-			busy_old_reg <= busy_old_next;
+         enc_old_reg <= enc_old_next;
-			form_old_reg <= form_old_next;
+         form_old_reg <= form_old_next;
-			
+         
-			charcnt_reg <= charcnt_next;
+         charcnt_reg <= charcnt_next;
-			lcd_newchar_reg<= lcd_newchar_next;
+         lcd_newchar_reg<= lcd_newchar_next;
-			lcd_newpos_reg<= lcd_newpos_next;
+         lcd_newpos_reg<= lcd_newpos_next;
-			lcd_data_reg <= lcd_data_next;
+         lcd_data_reg <= lcd_data_next;
 
-			freq_out_reg <= freq_out_next;
+         freq_out_reg <= freq_out_next;
-			
+         
-			state_reg <= state_next;
+         state_reg <= state_next;
-			ret_state_reg <= ret_state_next;
+         ret_state_reg <= ret_state_next;
-			
+         
-		end if;
+      end if;
-	end process proc1;
+   end process proc1;
-	
+   
- 
+   freq_out <= freq_out_reg;
-	
+   lcd_data <= lcd_data_reg;
-	freq_out <= freq_out_reg;
+   lcd_newchar <= lcd_newchar_reg;
-	lcd_data <= lcd_data_reg;
+   lcd_newpos <= lcd_newpos_reg;
-	lcd_newchar <= lcd_newchar_reg;
+   
-	lcd_newpos <= lcd_newpos_reg;
+   -- Next State logic process (combinational)
-	
+   NSL: process(digit_reg,enc_right,enc_ce,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, state_reg, ret_state_reg, enc_ce,enc_old_reg, form_old_reg, form) 
-	NSL: process(digit_reg,enc_right,enc_ce,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, busy_old_reg, state_reg, ret_state_reg, enc_ce,enc_old_reg, form_old_reg, form) 
+   begin
-	begin
+      -- To avoid latches the most signals are assigned with their previous value (Exceptions marked)
-		digit_next <= digit_reg;
+      digit_next <= digit_reg;
-		digpos_next <= digpos_reg;
+      digpos_next <= digpos_reg;
-		
+      
-		
+      btn_old_next <= btn_old_reg;
-		busy_old_next <= lcd_busy;
+      enc_old_next <= enc_old_reg;
-		btn_old_next <= btn_old_reg;
+      form_old_next <= form_old_reg;
-		enc_old_next <= enc_old_reg;
+      
-		form_old_next <= form_old_reg;
+      charcnt_next <= charcnt_reg;
+      lcd_newchar_next <= '0'; -- next newchar is always 0, becasue normally we dont want to send anything
+      lcd_newpos_next <= '0';  -- same for newpos
+      lcd_data_next <= lcd_data_reg;
 
-		
+      state_next <= state_reg;
-		charcnt_next <= charcnt_reg;
+      ret_state_next <= ret_state_reg;
-		lcd_newchar_next <= '0';
+      
-		lcd_newpos_next <= '0';
+      -- The next statement produces two warnings which can be safely ignored:
-		lcd_data_next <= lcd_data_reg;
+      -- xst:643 - The result of a <...>-bit multiplication is partially used...
+      -- Put together the frequency as a 17 bit vector (in hz) out of the single decimal places
+      freq_out_next <= resize(   resize(digit_reg(0), 4) 
+                               + resize(digit_reg(1) ,4)* 10
+                               + resize(digit_reg(2) ,7)* 100
+                               + resize(digit_reg(3) ,10) * 1000
+                               + resize(digit_reg(4) ,14) * 10000
+                              ,freq_res);
+               
+            
+      case state_reg is -- switch on current state
+            when S_WAIT => -- lcd is currently busy
+               if(lcd_busy = '0') then --lcd is no longer busy
+                  state_next<= ret_state_reg; -- return to state given by ret_state
+               end if;
+               
+            when S_FORM_PREF => -- print the form prefix
+               state_next <= S_WAIT;               -- always wait for lcd_busy=0 after this state
+               if(charcnt_reg < 7 ) then           -- not 8 characters written yet: Send characters
+                  charcnt_next <= charcnt_reg + 1; -- increase character position
+                  ret_state_next <= S_FORM_PREF;   -- return into this state after wait
+                  -- Output current character (Multiplexer). Implemented as an array lookup with cast from character to ascii value
+                  lcd_data_next <= to_unsigned(character'pos(str_form_pref(to_integer(resize(charcnt_reg,3)))),8);
+                  lcd_newchar_next <= '1';         -- signal the lcd driver that a new character is ready for writing
+               else -- all 8 characters written: Change adress to line 2 (as preparation for S_FREQ_PREF)
+                  charcnt_next <= (others => '0'); -- reset charcnt
+                  lcd_data_next <= x"40";          -- Start adress for line 2
+                  lcd_newpos_next <= '1';          -- signal the lcd driver that a new position is available
+                  ret_state_next <= S_FREQ_PREF;   -- continue with S_FREQ_PREF state
+               end if;
+               
+            when S_FREQ_PREF => -- print the frequency prefix/postfix
+               if(charcnt_reg < 15 ) then -- not all 16 characters written yet
+                  charcnt_next <= charcnt_reg + 1;
+                  state_next <= S_WAIT;
+                  ret_state_next <= S_FREQ_PREF;
+                  lcd_data_next <= to_unsigned(character'pos(str_freq_pref(to_integer(charcnt_reg))),8);
+                  lcd_newchar_next <= '1';
+               else -- all charcters written
+                  charcnt_next <= (others => '0');
+                  state_next <= S_FORM_CONT; -- print the Form content now
+               end if;
+                   
+            when S_FORM_CONT => -- print the form content
+               state_next <= S_WAIT;
+               ret_state_next <= S_FORM_CONT;
+               charcnt_next <= charcnt_reg + 1;
+               if(charcnt_reg < 1 ) then   -- Step 1: Set address
+                  lcd_data_next <= x"06";  -- adress character 7 on line 1
+                  lcd_newpos_next <= '1';
+               elsif(charcnt_reg < 9) then -- Step 2 (8x): Print a character of the form 
+                  lcd_data_next <= to_unsigned(character'pos(str_form(to_integer(form),to_integer(resize(charcnt_reg-1,3)))),8);
+                  lcd_newchar_next <= '1';
+               else -- Step 3: Set adress/cursor back to current digit
+                  charcnt_next <= (others => '0');
+                  lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
+                  lcd_newpos_next <= '1';
+                  ret_state_next <=  S_IDLE;
+               end if;
+               
+            when S_FREQ_CONT => -- print the frequency content
+               state_next <= S_WAIT;
+               if(charcnt_reg < 1 ) then   -- Step 1: Set address for current digit
+                  charcnt_next <= charcnt_reg + 1;
+                  ret_state_next <= S_FREQ_CONT;
+                  lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
+                  lcd_newpos_next <= '1';
+               elsif(charcnt_reg = 1) then -- Step 2: Print current digit
+                  charcnt_next <= charcnt_reg + 1;
+                  ret_state_next <= S_FREQ_CONT;
+                  lcd_data_next <= to_unsigned(character'pos('0'),8) + digit_reg(to_integer(digpos_reg));
+                  lcd_newchar_next <= '1';
+               else -- Step 3: Reset adress/cursor back to current digit (auto increment of display cannot be disabled)
+                  ret_state_next <= S_IDLE;
+                  charcnt_next <= (others => '0');
+                  lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
+                  lcd_newpos_next <= '1';
+               end if;
+               
+            when S_IDLE => -- Controller is idle and wait on user input
+               -- Update edge dectection helper registers:
+               btn_old_next <= enc_btn;
+               enc_old_next <= enc_ce;
+               form_old_next <= form;
 
-		
+               if(form /= form_old_reg) then -- form changed
-		state_next <= state_reg;
+                  state_next <= S_FORM_CONT; -- print form 
-		ret_state_next <= ret_state_reg;
+               elsif(enc_ce='1' and enc_old_reg ='0') then -- positive egde on encoder clock enable
-		
+                  if(enc_right='1') then     -- encoder was turned right
-		-- The next statement produces two warnings which can be safely ignored:
+                     if(digit_reg(to_integer(digpos_reg)) = to_unsigned(9,4)) then -- digit value = 9
-		-- xst:643 - The result of a <...>-bit multiplication is partially used...
+                        digit_next(to_integer(digpos_reg)) <= to_unsigned(0,4);    -- set digit value to 0
-		freq_out_next <= resize(
+                     else -- digit value < 9
-				  resize(digit_reg(0), 4) 
+                        digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) + 1; -- increase digit value
-			   + resize(digit_reg(1) ,4)* 10
+                     end if;
-				+ resize(digit_reg(2) ,7)* 100
+                  else  -- encoder was turned left
-		    	+ resize(digit_reg(3) ,10) * 1000
+                     if(digit_reg(to_integer(digpos_reg)) = to_unsigned(0,4)) then -- digit value = 0
-				+ resize(digit_reg(4) ,14) * 10000
+                        digit_next(to_integer(digpos_reg)) <= to_unsigned(9,4);    -- set digit value to 9
-				, 17);
+                     else -- digit value > 0
-				
+                        digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) -1; -- decrease digit value
-				
+                     end if;
-		case state_reg is
+                  end if;
-            when S_WAIT => -- switch on current state
+                  state_next <= S_FREQ_CONT; -- print frequency
-					if(lcd_busy = '0' and busy_old_reg ='1' ) then
+               elsif(enc_btn ='1' and btn_old_reg='0') then -- positive edge on push button
-						state_next<= ret_state_reg;
+                  if(digpos_reg = to_unsigned(4,3)) then    -- digit_pos = 4
-					end if;
+                     digpos_next <= to_unsigned(0,3);       -- set digit pos = 0
-					
+                  else -- digit pos < 4
-				when S_FORM_PREF =>
+                     digpos_next <= digpos_reg + 1; -- increase digit pos
-					state_next <= S_WAIT;
+                  end if;
-					if(charcnt_reg < 7 ) then
+                  state_next <= S_FREQ_CONT; -- print frequency (also updates the cursor position) 
-						charcnt_next <= charcnt_reg + 1;
+               end if;
-						ret_state_next <= S_FORM_PREF;
+               
-						lcd_data_next <= to_unsigned(character'pos(str_form_pref(to_integer(resize(charcnt_reg,3)))),8);
-						lcd_newchar_next <= '1';
-					else
-						charcnt_next <= (others => '0');
-						lcd_data_next <= x"40"; --Start adress for line 2
-						lcd_newpos_next <= '1';
-						ret_state_next <= S_FREQ_PREF;
-					end if;
-				when S_FREQ_PREF =>
-					if(charcnt_reg < 15 ) then
-						charcnt_next <= charcnt_reg + 1;
-						state_next <= S_WAIT;
-						ret_state_next <= S_FREQ_PREF;
-						lcd_data_next <= to_unsigned(character'pos(str_freq_pref(to_integer(charcnt_reg))),8);
-						lcd_newchar_next <= '1';
-					else
-						charcnt_next <= (others => '0');
-						state_next <= S_FORM_CONT;
-					end if;
-				
-				
-				when S_FORM_CONT => 
-					state_next <= S_WAIT;
-					ret_state_next <= S_FORM_CONT;
-					charcnt_next <= charcnt_reg + 1;
-					if(charcnt_reg < 1 ) then
-						lcd_data_next <= x"06"; --adress character 7 on line 1
-						lcd_newpos_next <= '1';
-					elsif(charcnt_reg < 9) then
-						lcd_data_next <= to_unsigned(character'pos(str_form(to_integer(form),to_integer(resize(charcnt_reg-1,3)))),8);
-						lcd_newchar_next <= '1';
-					else
-						charcnt_next <= (others => '0');
-						lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
-						lcd_newpos_next <= '1';
-						ret_state_next <=  S_IDLE;
-					end if;
-				when S_FREQ_CONT =>
-					state_next <= S_WAIT;
-					if(charcnt_reg < 1 ) then
-						charcnt_next <= charcnt_reg + 1;
-						ret_state_next <= S_FREQ_CONT;
-						lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
-						lcd_newpos_next <= '1';
-					elsif(charcnt_reg = 1) then 
-						charcnt_next <= charcnt_reg + 1;
-						ret_state_next <= S_FREQ_CONT;
-						lcd_data_next <= to_unsigned(character'pos('0'),8) + digit_reg(to_integer(digpos_reg));
-						lcd_newchar_next <= '1';
-					else
-						ret_state_next <= S_IDLE;
-						charcnt_next <= (others => '0');
-						lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
-						lcd_newpos_next <= '1';
-					end if;
-				when S_IDLE =>
-					btn_old_next <= enc_btn;
-					enc_old_next <= enc_ce;
-					form_old_next <= form;
-
-					if(form /= form_old_reg) then
-						state_next <= S_FORM_CONT;
-					elsif(enc_ce='1' and enc_old_reg ='0') then
-						if(enc_right='1') then
-							if(digit_reg(to_integer(digpos_reg)) = to_unsigned(9,4)) then
-								digit_next(to_integer(digpos_reg)) <= to_unsigned(0,4);
-							else
-								digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) + 1;
-							end if;
-						else
-							if(digit_reg(to_integer(digpos_reg)) = to_unsigned(0,4)) then
-								digit_next(to_integer(digpos_reg)) <= to_unsigned(9,4);
-							else
-								digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) -1;
-							end if;
-						end if;
-						state_next <= S_FREQ_CONT;
-					elsif(enc_btn ='1' and btn_old_reg='0') then
-						if(digpos_reg = to_unsigned(4,3)) then
-							digpos_next <= to_unsigned(0,3);
-						else
-							digpos_next <= digpos_reg + 1;
-						end if;
-						state_next <= S_FREQ_CONT;
-					end if;
-					
-                     
             when others => null; -- do nothing, if we are in a different state
-        end case;		
+        end case;      
-	
+   
-	
+   
-	end process NSL;
+   end process NSL;
-	
+   
 end Behavioral;
 

controller_tb.vhd

@@ -1,37 +1,15 @@
---------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer:
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
---
+-- Authors:        Aaron Schmocker & Timo Lang
--- Create Date:   20:08:51 06/06/2016
+-- License:        GPL v3
--- Design Name:   
+-- Create Date:    18:02:40 06/19/2016
--- Module Name:   /home/timo/workspace/vhdl-yasg/controller_tb.vhd
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: controller
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
 --------------------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 USE ieee.numeric_std.ALL;
  
+
 ENTITY controller_tb IS
 END controller_tb;
  
@@ -43,13 +21,14 @@ ARCHITECTURE behavior OF controller_tb IS
     PORT(
          clk : IN  std_logic;
          rst : IN  std_logic;
-         enc_updown : IN  std_logic;
+         enc_right : IN  std_logic;
          enc_ce : IN  std_logic;
          enc_btn : IN  std_logic;
-         enc_err : IN  std_logic;
+         form : IN  unsigned(1 downto 0);
          lcd_busy : IN  std_logic;
          lcd_data : OUT  unsigned(7 downto 0);
          lcd_newchar : OUT  std_logic;
+         lcd_newpos : OUT  std_logic;
          freq_out : OUT  unsigned(16 downto 0)
         );
     END COMPONENT;
@@ -58,19 +37,20 @@ ARCHITECTURE behavior OF controller_tb IS
    --Inputs
    signal clk : std_logic := '0';
    signal rst : std_logic := '0';
-   signal enc_updown : std_logic := '0';
+   signal enc_right : std_logic := '0';
    signal enc_ce : std_logic := '0';
    signal enc_btn : std_logic := '0';
-   signal enc_err : std_logic := '0';
+   signal form : unsigned(1 downto 0) := (others => '0');
    signal lcd_busy : std_logic := '0';
 
  	--Outputs
    signal lcd_data : unsigned(7 downto 0);
    signal lcd_newchar : std_logic;
+   signal lcd_newpos : std_logic;
    signal freq_out : unsigned(16 downto 0);
 
    -- Clock period definitions
-   constant clk_period : time := 10 ns;
+   constant clk_period : time := 20 ns; --50mhz
  
 BEGIN
  
@@ -78,13 +58,14 @@ BEGIN
    uut: controller PORT MAP (
           clk => clk,
           rst => rst,
-          enc_updown => enc_updown,
+          enc_right => enc_right,
           enc_ce => enc_ce,
           enc_btn => enc_btn,
-          enc_err => enc_err,
+          form => form,
           lcd_busy => lcd_busy,
           lcd_data => lcd_data,
           lcd_newchar => lcd_newchar,
+          lcd_newpos => lcd_newpos,
           freq_out => freq_out
         );
 
@@ -102,13 +83,77 @@ BEGIN
    stim_proc: process
    begin		
       -- hold reset state for 100 ns.
+      rst <= '1';
       wait for 100 ns;	
+      rst <= '0';
+      
+      lcd_busy<='1'; --simulate lcd busy
+      wait for 200 ns;
+      lcd_busy<='0'; 
+      
+      wait for 1000 ns;
+      wait until lcd_newchar = '1';
+      lcd_busy<='1'; --simulate lcd busy
+      wait for 150 ns;
+      lcd_busy<='0'; 
+      
+      wait for 400 ns;
+      --init should be finished here
+      
+      --Test encoder turn right
+      enc_right <='1';
+      enc_ce <= '1';
+      wait for clk_period;
+      enc_ce <= '0';
+      wait for 300 ns; 
+     
+      -- Now the same but with lcd_busy
+      enc_ce <= '1';
+      wait for clk_period;
+      enc_ce <= '0';
+      wait until lcd_newpos = '1';
+      lcd_busy<='1'; --simulate lcd busy
+      wait for 150 ns;
+      lcd_busy<='0'; 
+      wait for 300 ns;
+      
+      --Test encoder turn left
+      enc_right <= '0';
+      enc_ce <= '1';
+      wait for clk_period;
+      enc_ce <= '0';
+      wait until lcd_newpos = '1';
+      lcd_busy<='1'; --simulate lcd busy
+      wait for 150 ns;
+      lcd_busy<='0'; 
+      wait for 300 ns;
+      
+      --Test button press
+      enc_btn <= '1';
+      wait for clk_period;
+      enc_btn <= '0';
+      wait for 150 ns;
+      
+      --Test another turn left
+      enc_ce <= '1';
+      wait for clk_period;
+      enc_ce <= '0';
+      wait until lcd_newpos = '1';
+      lcd_busy<='1'; --simulate lcd busy
+      wait for 150 ns;
+      lcd_busy<='0'; 
+      wait for 300 ns;
+      
+      
+      
+      
+      
+      
+      
+      
+      
 
-      wait for clk_period*10;
+      
-		
-		rst<= '0';
-		lcd_busy <= '0';
-		
 
       -- insert stimulus here 
 

dds.vhd

@@ -1,22 +1,11 @@
 ----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer: 
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
--- 
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    11:09:53 05/16/2016 
--- Design Name: 
--- Module Name:    dds - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
@@ -24,78 +13,84 @@ use IEEE.MATH_REAL.ALL;
 use work.helpers.all;
 
 entity dds is
-    Generic (clk_freq: natural:= 50000000;
+    Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz
-             freq_res: natural:=17; -- width of frequency input (log2(max_freq))
+             freq_res: natural:=17;        -- width of frequency input (log2(max_freq))
-             adc_res: natural:=12; -- width of the ouput signal (=adc resolution)
+             adc_res: natural:=12;         -- width of the output signal (=adc resolution)
-             acc_res: natural:=32; -- width of the phase accumulator
+             acc_res: natural:=32;         -- width of the phase accumulator
-             phase_res: natural:=10); -- effective phase resolution for sin lookup table
+             phase_res: natural:=10);      -- effective phase resolution for sin lookup table
-    Port ( clk : in  STD_LOGIC;
+    Port ( clk : in  STD_LOGIC;                        -- Clock input
-           freq : in  unsigned (freq_res-1 downto 0);
+           freq : in  unsigned (freq_res-1 downto 0);  -- Frequenzy input (treshould in Hz)
-           form : in  unsigned (1 downto 0);
+           form : in  unsigned (1 downto 0);           -- Form selection (00=Rectancle, 01=Sawtooth, 10=Triangle, 11=Sine)
-           amp : out  unsigned (adc_res-1 downto 0));
+           amp : out  unsigned (adc_res-1 downto 0));  -- Signal Output (Amplitude)
 end dds;
 
 architecture Behavioral of dds is   
-    signal m, idx : unsigned(acc_res -1  downto 0):= (others => '0');   
+    signal m, idx : unsigned(acc_res -1  downto 0):= (others => '0');            -- phase jump size and accumulator (see Fundamentals of Direct Digital Synthesis for details about their function) 
-    signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0');  
+    signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0');        -- relevant (=leftmost) bits of the phase acccumulator  
-    signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0);
+    signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0); -- the current amplitudes of all 4 signal forms
     
+    -- Function to genenerate and store the sine wave in the rom.
+    -- Current code: Only store 1/4 of a sine wave and use symmetries.
+    -- Uncommented code: Store the entire sine wave (decrease adc_width to 8)
     type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0);
-	 --type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
+    --type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
     function gen_sin_wave return storage is
         variable temp : storage;
         begin
-            forLoop: for i in 0 to temp'high loop
+            forLoop: for i in 0 to temp'high loop -- for each element in the array
                temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1);
-					--temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1)  + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);
+               --temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1)  + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);               
-            	
+            end loop;
-				end loop;
         return temp;
     end function gen_sin_wave;
-    constant sin_wave : storage := gen_sin_wave;
+    constant sin_wave : storage := gen_sin_wave; -- rom for sin wave
    
 begin
 
+    -- Calculate jump size according to input frequency
     -- m = fout*(2^n)/fclk = fout*((2^n)*(2^k)/fclk)/(2^k)   with k=ceil(log2(fclk)), n=acc_res
-	 m <= resize(  (resize(freq,64) 
+    m <= resize(  (resize(freq,64) 
-					   * 
+                  * 
-					   (shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq)) 
+                  (shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq)) 
-					  /to_unsigned(2**log2_int(clk_freq),64),acc_res);
+                 /to_unsigned(2**log2_int(clk_freq),64),acc_res);
 
-
+    -- Amplitude of the square wave
-    amp_rect <= to_unsigned(0,adc_res) when idx(acc_res-1)='0' else 
+    amp_rect <= to_unsigned(0,adc_res) when idx(acc_res-1)='0' else  -- 0 for half of the time
-                to_unsigned((2**adc_res)-1,adc_res);
+                to_unsigned((2**adc_res)-1,adc_res); --1 for the rest
     
-    amp_saw <=  idx(acc_res -1 downto acc_res - adc_res);
+    -- Amplitude of the sawtooth wave
-	 
+    amp_saw <=  idx(acc_res -1 downto acc_res - adc_res); -- Exactly the value of the uppermost bits of the phase acc
-	
+    
-	 amp_tria <= idx(acc_res -2 downto acc_res - adc_res) & "0"
+    -- Amplitude of the triangle wave 
-                 when idx(acc_res-1)='0' else 
+    amp_tria <= idx(acc_res -2 downto acc_res - adc_res - 1) -- The value of the uppermost bits, except the uppermost one (= double the frequency)
-					  ((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res) & "0");
+                when idx(acc_res-1)='0' else -- during half of the time
+                ((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res - 1)); -- and the complement, the rest of the time
 
-	 
+   
-	 
+    idx_phase <= idx(acc_res -1 downto acc_res - phase_res); -- take only the uppermost bits for the sine lookup
-	 idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
+    
-	 
+    -- Amplitude of the sine wave
-	 --amp_sin <= sin_wave(to_integer(idx_phase));
+    -- Code if we had stored the whole sinewave:
-	 amp_sin <=  to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else
+    --  amp_sin <= sin_wave(to_integer(idx_phase));
+    -- Current Code (only 1/4 of the sine wave stored)
+    amp_sin <=  to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else
                 to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="01" else
                 to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="10" else
                 to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0)));
-					 
+    
-					 
+    -- Output the selected amplitue using a multiplexer (00=Rectancle, 01=Sawtooth, 10=Triangle, 11=Sine)                  
-    with form select amp <= amp_rect when "00",
+    amp <= to_unsigned(0,adc_res)  when freq = to_unsigned(0,freq_res) else              
-                            amp_saw when "01",
+                            amp_rect when form = "00" else
-                            amp_tria when "10",
+                            amp_saw when form ="01" else
-                            amp_sin when others;
+                            amp_tria when form = "10" else
+                            amp_sin;
                             
+    -- Process for the phase accumulator (sequential)                         
     P1: process(clk) 
     begin
         if(rising_edge(clk)) then
-            idx <= (idx+m);
+            idx <= (idx+m); -- increment phase accumulator according to jump size. overflow is wanted.
         end if;
     end process P1;
-
-
 end Behavioral;
 

dds_tb.vhd

@@ -1,30 +1,11 @@
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
+-- Create Date:    11:35:57 05/16/2016
 --------------------------------------------------------------------------------
--- Company: 
+
--- Engineer:
---
--- Create Date:   11:35:57 05/16/2016
--- Design Name:   
--- Module Name:   /home/timo/vhdl-yasg/dds_tb.vhd
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: dds
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.numeric_std.ALL;
@@ -51,7 +32,7 @@ ARCHITECTURE behavior OF dds_tb IS
    signal freq : unsigned(16 downto 0) := (others => '0');
    signal form : unsigned(1 downto 0) := (others => '0');
 
- 	--Outputs
+    --Outputs
    signal amp : unsigned(11 downto 0);
 
    -- Clock period definitions
@@ -59,7 +40,7 @@ ARCHITECTURE behavior OF dds_tb IS
  
 BEGIN
  
-	-- Instantiate the Unit Under Test (UUT)
+   -- Instantiate the Unit Under Test (UUT)
    uut: dds PORT MAP (
           clk => clk,
           freq => freq,
@@ -70,18 +51,18 @@ BEGIN
    -- Clock process definitions
    clk_process :process
    begin
-		clk <= '0';
+      clk <= '0';
-		wait for clk_period/2;
+      wait for clk_period/2;
-		clk <= '1';
+      clk <= '1';
-		wait for clk_period/2;
+      wait for clk_period/2;
    end process;
  
 
    -- Stimulus process
    stim_proc: process
-   begin		
+   begin      
       -- hold reset state for 100 ns.
-      wait for 100 ns;	
+      wait for 100 ns;   
 
    
  

helpers.vhd

@@ -1,3 +1,10 @@
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:          GPL v3
+-- Create Date:    12:59:01 05/16/2016 
+----------------------------------------------------------------------------------
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -6,11 +13,9 @@ use IEEE.NUMERIC_STD.ALL;
 package helpers is
     --helper function to calculate the log2 (truncated) of a integer
     function log2_int(n:natural) return natural; 
-    function divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
 end helpers;
 
 
-
 package body helpers is
     function log2_int(n:natural) return natural is
         begin
@@ -19,28 +24,5 @@ package body helpers is
           end if;
           return 1; --since we can no longer divide n, return 1
     end log2_int;
-    
-    --Source: http://vhdlguru.blogspot.ch/2010/03/vhdl-function-for-division-two-signed.html
-    function  divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
-    variable a1 : unsigned(a'length-1 downto 0):=a;
-    variable b1 : unsigned(b'length-1 downto 0):=b;
-    variable p1 : unsigned(b'length downto 0):= (others => '0');
-    variable i : integer:=0;
-
-    begin
-        for i in 0 to b'length-1 loop
-            p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
-            p1(0) := a1(a'length-1);
-            a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
-            p1 := p1-b1;
-            if(p1(b'length-1) ='1') then
-                a1(0) :='0';
-                p1 := p1+b1;
-            else
-                a1(0) :='1';
-            end if;
-        end loop;
-        return a1;
-    end divide;
 end helpers;
 

io.ucf

@@ -1,3 +1,11 @@
+#---------------------------------------------------------------------------------
+#- Project:        YASG (Yet another signal generator)
+#- Project Page:   https://github.com/id101010/vhdl-yasg/
+#- Authors:        Aaron Schmocker & Timo Lang
+#- License:		    GPL v3
+#- Create Date:    16:23:12 05/20/2016 
+#---------------------------------------------------------------------------------
+
 NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
 NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
 

iseconfig/filter.filter

@@ -6,8 +6,8 @@
 <filters xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation='filter.xsd'>
 <filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_8</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
 <filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_6</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
-<filter task="xst" file="Xst" num="643" type="warning"><arg index="1" match_type="wildcard">/home/timo/workspace/vhdl-yasg/controller.vhd</arg><arg index="2" match_type="wildcard">169</arg><arg index="3" match_type="wildcard">*</arg><arg index="4" match_type="wildcard">*</arg><arg index="5" match_type="wildcard">17</arg></filter>
+<filter task="xst" file="Xst" num="643" type="warning"><arg index="1">/home/timo/workspace/vhdl-yasg/controller.vhd</arg><arg index="2" match_type="wildcard">*</arg><arg index="3" match_type="wildcard">*</arg><arg index="4" match_type="wildcard">*</arg><arg index="5">17</arg></filter>
 <filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_7</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
-<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_reg_0</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
+<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_reg_0</arg><arg index="2" match_type="wildcard">*</arg><arg index="3">controller</arg></filter>
 <filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">lcd_data_reg_7</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
 </filters>

lcd_driver.vhd

@@ -1,45 +1,15 @@
 ----------------------------------------------------------------------------------
--- This program is free software: you can redistribute it and/or modify
+-- Project:        YASG (Yet another signal generator)
--- it under the terms of the GNU General Public License as published by
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
--- the Free Software Foundation, either version 3 of the License, or
+-- Authors:        Aaron Schmocker & Timo Lang
--- (at your option) any later version.
+-- License:        GPL v3
---
+-- Create Date:    19:29:54 05/09/2016 
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------------
--- Company:         Berner Fachhochschule
--- Engineer:        Aaron Schmocker
--- 
--- Create Date:     19:29:54 05/09/2016 
--- Design Name: 
--- Module Name:     lcddriver - Behavioral 
--- Project Name:    yasg
--- Target Devices:  Spartan-3am Board
--- Tool versions: 
--- Description:     This file is part of the yasg project
---
--- Dependencies: 
---
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity lcd_driver is
     generic (   NBITS           : natural := 21;        -- counter bit size
@@ -48,15 +18,15 @@ entity lcd_driver is
                 wait_between    : natural := 37;        -- wait 37us
                 wait_pause      : natural := 1520);     -- wait 1.52ms
                 
-    Port (  clk : in STD_LOGIC;                         -- Systemclock (50MHz)
+    Port (  clk : in STD_LOGIC;                         -- Clock Input
-            reset : in STD_LOGIC;                       -- Initialize display controller
+            reset : in STD_LOGIC;                       -- High active, async reset
-            data : in  STD_LOGIC_VECTOR (7 downto 0);   -- either one ascii char (8bit) or new cursor position (0-31)
+            data : in  STD_LOGIC_VECTOR (7 downto 0);   -- either one ascii char (8bit) or new cursor position/adress
             new_character : in  STD_LOGIC;              -- a new character is available on the data bus
             new_pos : in  STD_LOGIC;                    -- a new cursor position is available on the data bus
-            busy : out STD_LOGIC;                       -- 1 when sending stuff
+            busy : out STD_LOGIC;                       -- output which signals that the driver/lcd is currently busy
-            lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd databus
+            lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd output: databus
-            lcd_en : out STD_LOGIC;                     -- lcd enable
+            lcd_en : out STD_LOGIC;                     -- lcd output: enable
-            lcd_rs : out STD_LOGIC);                    -- lcd register select
+            lcd_rs : out STD_LOGIC);                    -- lcd output: register select
 end lcd_driver;
 
 architecture Behavioral of lcd_driver is
@@ -215,15 +185,15 @@ begin
                 next_lcd_rs <= '0';
                 
                 if(new_character = '1') then -- send data
-						  next_ret_state <= DONE;
+                    next_ret_state <= DONE;
-						  next_state <= WAITING1;
+                    next_state <= WAITING1;
                     next_lcd_rs <= '1';
                     next_counter <= (others => '0');
                     next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS); 
                     next_lcd_db <= data; 
                 elsif(new_pos = '1') then -- new address
-						  next_state <= WAITING1;
+                    next_state <= WAITING1;
-						  next_ret_state <= DONE;
+                    next_ret_state <= DONE;
                     next_lcd_db <= '1' & data(6 downto 0);
                     next_counter <= (others => '0');
                     next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);

lcd_driver_tb.vhd

@@ -1,37 +1,14 @@
---------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer:
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
---
+-- Authors:        Aaron Schmocker & Timo Lang
--- Create Date:   21:11:41 05/16/2016
+-- License:        GPL v3
--- Design Name:   
+-- Create Date:    21:11:41 05/16/2016
--- Module Name:   /home/aaron/Dokumente/STUDIUM/SEM6/EloSys/EloSysDigital/Projekt/vhdl-yasg/lcd_driver_tb.vhd
+----------------------------------------------------------------------------------
--- Project Name:  yasg
+
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: lcd_driver
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
  
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
 ENTITY lcd_driver_tb IS
 END lcd_driver_tb;
  
@@ -42,15 +19,14 @@ ARCHITECTURE behavior OF lcd_driver_tb IS
     COMPONENT lcd_driver
     PORT(
          clk : IN  std_logic;
+         busy : out STD_LOGIC; 
          reset : IN  std_logic;
          data : IN  std_logic_vector(7 downto 0);
          new_character : IN  std_logic;
          new_pos : IN  std_logic;
-         auto_incr_cursor : IN  std_logic;
          lcd_db : OUT  std_logic_vector(7 downto 0);
          lcd_en : OUT  std_logic;
-         lcd_rw : OUT  std_logic;
+         lcd_rs : OUT std_logic
-         lcd_rs : OUT  std_logic
         );
     END COMPONENT;
     
@@ -61,58 +37,73 @@ ARCHITECTURE behavior OF lcd_driver_tb IS
    signal data : std_logic_vector(7 downto 0) := (others => '0');
    signal new_character : std_logic := '0';
    signal new_pos : std_logic := '0';
-   signal auto_incr_cursor : std_logic := '0';
 
- 	--Outputs
+    --Outputs
    signal lcd_db : std_logic_vector(7 downto 0);
    signal lcd_en : std_logic;
-   signal lcd_rw : std_logic;
    signal lcd_rs : std_logic;
+   signal busy : std_logic;
 
    -- Clock period definitions
    constant clk_period : time := 20 ns;
  
 BEGIN
  
-	-- Instantiate the Unit Under Test (UUT)
+   -- Instantiate the Unit Under Test (UUT)
    uut: lcd_driver PORT MAP (
           clk => clk,
           reset => reset,
           data => data,
           new_character => new_character,
           new_pos => new_pos,
-          auto_incr_cursor => auto_incr_cursor,
           lcd_db => lcd_db,
           lcd_en => lcd_en,
-          lcd_rw => lcd_rw,
+          lcd_rs => lcd_rs,
-          lcd_rs => lcd_rs
+          busy => busy
         );
 
    -- Clock process definitions
    clk_process :process
    begin
-		clk <= '0';
+      clk <= '0';
-		wait for clk_period/2;
+      wait for clk_period/2;
-		clk <= '1';
+      clk <= '1';
-		wait for clk_period/2;
+      wait for clk_period/2;
    end process;
  
 
    -- Stimulus process
    stim_proc: process
-   begin		
+   begin      
    
       reset <= '1';
       wait for 100 ns;  -- hold reset state for 100 ns.
       reset <= '0';
-      
-      -- Apply Data 
-      --data = ''
 
-      wait for clk_period*10;
+      wait for 50ms;
       
-      -- insert stimulus here 
 
+      -- test sending character
+      data <= "11111111";
+      new_character <= '1';
+      new_pos <= '0';
+
+      wait until busy = '0';
+      wait for 10ms;
+      
+      -- test sending character
+      data <= "10101010";
+      new_character <= '0';
+      new_pos <= '1';
+      
+      wait until busy = '0';
+      wait for 10ms;
+      
+      -- Reset
+      data <= "00000000";
+      new_character <= '0';
+      new_pos <= '0';
+      
       wait;
    end process;
 

rotary.vhd

@@ -1,49 +1,105 @@
------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
---
+-- Project:        YASG (Yet another signal generator)
--- Decoder für Drehgeber
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
---
+-- Authors:        Aaron Schmocker & Timo Lang
------------------------------------------------------------------------------
+-- License:        GPL v3
+-- Create Date:    19:07:22 05/23/2016 
+----------------------------------------------------------------------------------
  
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
  
 entity rotary_dec is
-    Port ( clk      : in std_logic;         -- Systemtakt
+    Generic (clk_freq: natural:= 50000000;  -- Clock frequency in hz
-           A        : in std_logic;         -- Spur A
+             debounce_time: natural := 10);  -- Debounce time in ms
-           B        : in std_logic;         -- Spur B
+    Port ( clk      : in std_logic;         -- Clock Input
-           right    : out std_logic;        -- Zaehlrichtung
+           A        : in std_logic;         -- Signal A
-           ce       : out std_logic);        -- Clock Enable
+           B        : in std_logic;         -- Signal B
+           btn      : in std_logic;         -- Button Input
+           btn_deb  : out std_logic;        -- Button Output Debonced
+           enc_right: out std_logic;        -- Direction Output: 1=right
+           enc_ce   : out std_logic);       -- Clock Enable Output for signal above
 
 end rotary_dec;
  
 architecture Behavioral of rotary_dec is
  
-signal a_in, b_in, a_old, b_old: std_logic;
+signal a_old, b_old: std_logic := '0';      -- Registers for edge detection on debounced A, B signals
+signal a_debounced_reg, a_debounced_next,   -- Registers for debouncing A, B signals
+       b_debounced_reg, b_debounced_next : std_logic := '0';
+signal btn_reg, btn_next: std_logic :='0';  -- Registers for debouncing Button Press signal
+signal counter_a_reg, counter_a_next,       -- Counters to smooth chittering = debounce signals
+       counter_b_reg, counter_b_next,
+       counter_btn_reg, counter_btn_next: unsigned(23 downto 0) := (others => '0');
+constant count_max: unsigned(23 downto 0) := to_unsigned(clk_freq / (1000 / debounce_time),24); --Number of cycles during which a signal can't change it's value 50mhz*10ms= 500000 cycles   
  
 begin
  
--- Abtastung und Verzoegerung der Quadratursignale
+-- State register process (sequential)
- 
 process(clk)
 begin
   if rising_edge(clk) then
-    a_old <= a_in;
+    counter_a_reg <= counter_a_next;
-    a_in  <= A;
+    counter_b_reg <= counter_b_next;
-    b_old <= b_in;
+    counter_btn_reg <= counter_btn_next;
-    b_in  <= B;
+    
+    a_debounced_reg <= a_debounced_next;
+    b_debounced_reg <= b_debounced_next;
+    btn_reg <= btn_next;
+    
+    a_old <= a_debounced_reg;
+    b_old <= b_debounced_reg;
   end if;
 end process;
+
+-- Debounce process (combinational)
+process(A,B, a_debounced_reg, b_debounced_reg, counter_a_reg, counter_b_reg, btn_reg, btn, counter_btn_reg) 
+begin
+   
+   -- If signal a has changed (edge detection) and enough time passed since the last change
+   if(A /= a_debounced_reg and counter_a_reg > count_max) then
+      a_debounced_next <= A; -- accept change
+      counter_a_next <= (others => '0'); -- reset counter
+   else -- singal has not changed, or not enough time has passed
+      a_debounced_next <= a_debounced_reg; -- keep old signal value
+      counter_a_next <= counter_a_reg + 1; -- increase counter by one
+   end if;
+   
+   -- Same as above for signal B
+   if(B /= b_debounced_reg and counter_b_reg > count_max) then
+      b_debounced_next <= B;
+      counter_b_next <= (others => '0');
+   else
+      b_debounced_next <= b_debounced_reg;
+      counter_b_next <= counter_b_reg + 1;
+   end if;
+   
+   -- Same as above for button press signal
+   if(btn /= btn_reg and counter_btn_reg > count_max) then
+      btn_next <= btn;
+      counter_btn_next <= (others => '0');
+   else
+      btn_next <= btn_reg;
+      counter_btn_next <= counter_btn_reg + 1;
+   end if;
+
+end process;
+
+
+btn_deb <= btn_reg; --Output debounced btn reg
  
--- Dekodierung der Ausgaenge
+-- Ouput decode for Rotary Signals (A,B)
- 
+process(a_debounced_reg, b_debounced_reg, a_old, b_old)
-process(a_in, b_in, a_old, b_old)
 variable state: std_logic_vector(3 downto 0);
 begin
-  state := a_in & b_in & a_old & b_old;
+  state := a_debounced_reg & b_debounced_reg & a_old & b_old; -- Concat to vector
   case state is
-    when "0001" => right <= '0'; ce <= '1';
+    when "0001" => enc_right <= '0'; enc_ce <= '1';
-    when "0010" => right <= '1'; ce <= '1';
+    when "0010" => enc_right <= '1'; enc_ce <= '1';
-    when others => right <= '0'; ce <= '0';
+    when others => enc_right <= '0'; enc_ce <= '0';
+    -- If you want a finer resolution you can simply add more cases here.
+    -- In our case we only have 1 case for left, and one for right, which works fine.
   end case;
 end process;
  

rotary_dec.sym

@@ -1,24 +1,30 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <symbol version="7" name="rotary_dec">
     <symboltype>BLOCK</symboltype>
-    <timestamp>2016-6-10T10:5:37</timestamp>
+    <timestamp>2016-6-13T11:22:41</timestamp>
-    <pin polarity="Input" x="0" y="-160" name="clk" />
+    <pin polarity="Input" x="0" y="-224" name="clk" />
-    <pin polarity="Input" x="0" y="-96" name="A" />
+    <pin polarity="Input" x="0" y="-160" name="A" />
-    <pin polarity="Input" x="0" y="-32" name="B" />
+    <pin polarity="Input" x="0" y="-96" name="B" />
-    <pin polarity="Output" x="384" y="-32" name="ce" />
+    <pin polarity="Input" x="0" y="-32" name="btn" />
-    <pin polarity="Output" x="384" y="-96" name="right" />
+    <pin polarity="Output" x="384" y="-32" name="enc_ce" />
+    <pin polarity="Output" x="384" y="-96" name="enc_right" />
+    <pin polarity="Output" x="384" y="-160" name="btn_deb" />
     <graph>
-        <rect width="256" x="64" y="-192" height="192" />
+        <rect width="256" x="64" y="-256" height="256" />
-        <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
+        <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-264" type="symbol" />
-        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin clk" />
+        <line x2="0" y1="-224" y2="-224" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin A" />
         <line x2="0" y1="-160" y2="-160" x1="64" />
-        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin A" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin B" />
         <line x2="0" y1="-96" y2="-96" x1="64" />
-        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin B" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin btn" />
         <line x2="0" y1="-32" y2="-32" x1="64" />
-        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin ce" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin enc_ce" />
         <line x2="384" y1="-32" y2="-32" x1="320" />
-        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin right" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin enc_right" />
         <line x2="384" y1="-96" y2="-96" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin btn_deb" />
+        <line x2="384" y1="-160" y2="-160" x1="320" />
     </graph>
 </symbol>

rotary_tb.vhd

@@ -0,0 +1,77 @@
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
+-- Create Date:    13:41:21 06/19/2016
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+ENTITY rotary_tb IS
+END rotary_tb;
+ 
+ARCHITECTURE behavior OF rotary_tb IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT rotary_dec
+    PORT(
+         clk : IN  std_logic;
+         A : IN  std_logic;
+         B : IN  std_logic;
+         btn : IN  std_logic;
+         btn_deb : OUT  std_logic;
+         enc_right : OUT  std_logic;
+         enc_ce : OUT  std_logic
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk : std_logic := '0';
+   signal A : std_logic := '0';
+   signal B : std_logic := '0';
+   signal btn : std_logic := '0';
+
+    --Outputs
+   signal btn_deb : std_logic;
+   signal enc_right : std_logic;
+   signal enc_ce : std_logic;
+
+   -- Clock period definitions
+   constant clk_period : time := 10 ns;
+ 
+BEGIN
+ 
+   -- Instantiate the Unit Under Test (UUT)
+   uut: rotary_dec PORT MAP (
+          clk => clk,
+          A => A,
+          B => B,
+          btn => btn,
+          btn_deb => btn_deb,
+          enc_right => enc_right,
+          enc_ce => enc_ce
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+      clk <= '0';
+      wait for clk_period/2;
+      clk <= '1';
+      wait for clk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin      
+    
+
+      wait;
+   end process;
+
+END;

simulate_controller.wcfg

@@ -0,0 +1,87 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="/home/timo/workspace/vhdl-yasg/controller_tb_isim_beh.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="controller_tb" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="17" />
+   <wvobject fp_name="/controller_tb/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/rst" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst</obj_property>
+      <obj_property name="ObjectShortName">rst</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/enc_right" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enc_right</obj_property>
+      <obj_property name="ObjectShortName">enc_right</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/enc_ce" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enc_ce</obj_property>
+      <obj_property name="ObjectShortName">enc_ce</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/enc_btn" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enc_btn</obj_property>
+      <obj_property name="ObjectShortName">enc_btn</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/form" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">form[1:0]</obj_property>
+      <obj_property name="ObjectShortName">form[1:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/lcd_busy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">lcd_busy</obj_property>
+      <obj_property name="ObjectShortName">lcd_busy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/lcd_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">lcd_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">lcd_data[7:0]</obj_property>
+      <obj_property name="Radix">ASCIIRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/lcd_newchar" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">lcd_newchar</obj_property>
+      <obj_property name="ObjectShortName">lcd_newchar</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/lcd_newpos" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">lcd_newpos</obj_property>
+      <obj_property name="ObjectShortName">lcd_newpos</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/freq_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">freq_out[16:0]</obj_property>
+      <obj_property name="ObjectShortName">freq_out[16:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/clk_period" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_period</obj_property>
+      <obj_property name="ObjectShortName">clk_period</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/uut/state_reg" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">state_reg</obj_property>
+      <obj_property name="ObjectShortName">state_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/uut/ret_state_reg" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">ret_state_reg</obj_property>
+      <obj_property name="ObjectShortName">ret_state_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/uut/digpos_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">digpos_reg[2:0]</obj_property>
+      <obj_property name="ObjectShortName">digpos_reg[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/uut/charcnt_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">charcnt_reg[3:0]</obj_property>
+      <obj_property name="ObjectShortName">charcnt_reg[3:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/controller_tb/uut/digit_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">digit_reg[0:7]</obj_property>
+      <obj_property name="ObjectShortName">digit_reg[0:7]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+</wave_config>

simulate_display_init.wcfg

@@ -11,7 +11,7 @@
          </top_modules>
       </db_ref>
    </db_ref_list>
-   <WVObjectSize size="19" />
+   <WVObjectSize size="17" />
    <wvobject fp_name="/lcd_driver_tb/clk" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">clk</obj_property>
       <obj_property name="ObjectShortName">clk</obj_property>
@@ -20,6 +20,14 @@
       <obj_property name="ElementShortName">reset</obj_property>
       <obj_property name="ObjectShortName">reset</obj_property>
    </wvobject>
+   <wvobject fp_name="/lcd_driver_tb/uut/busy" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">busy</obj_property>
+      <obj_property name="ObjectShortName">busy</obj_property>
+   </wvobject>
+   <wvobject fp_name="/lcd_driver_tb/lcd_db" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">lcd_db[7:0]</obj_property>
+      <obj_property name="ObjectShortName">lcd_db[7:0]</obj_property>
+   </wvobject>
    <wvobject fp_name="/lcd_driver_tb/data" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">data[7:0]</obj_property>
       <obj_property name="ObjectShortName">data[7:0]</obj_property>
@@ -32,23 +40,11 @@
       <obj_property name="ElementShortName">new_pos</obj_property>
       <obj_property name="ObjectShortName">new_pos</obj_property>
    </wvobject>
-   <wvobject fp_name="/lcd_driver_tb/auto_incr_cursor" type="logic" db_ref_id="1">
+   <wvobject fp_name="/lcd_driver_tb/uut/lcd_en" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">auto_incr_cursor</obj_property>
-      <obj_property name="ObjectShortName">auto_incr_cursor</obj_property>
-   </wvobject>
-   <wvobject fp_name="/lcd_driver_tb/lcd_db" type="array" db_ref_id="1">
-      <obj_property name="ElementShortName">lcd_db[7:0]</obj_property>
-      <obj_property name="ObjectShortName">lcd_db[7:0]</obj_property>
-   </wvobject>
-   <wvobject fp_name="/lcd_driver_tb/lcd_en" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">lcd_en</obj_property>
       <obj_property name="ObjectShortName">lcd_en</obj_property>
    </wvobject>
-   <wvobject fp_name="/lcd_driver_tb/lcd_rw" type="logic" db_ref_id="1">
+   <wvobject fp_name="/lcd_driver_tb/uut/lcd_rs" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">lcd_rw</obj_property>
-      <obj_property name="ObjectShortName">lcd_rw</obj_property>
-   </wvobject>
-   <wvobject fp_name="/lcd_driver_tb/lcd_rs" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">lcd_rs</obj_property>
       <obj_property name="ObjectShortName">lcd_rs</obj_property>
    </wvobject>
@@ -72,10 +68,6 @@
       <obj_property name="ElementShortName">next_ret_state</obj_property>
       <obj_property name="ObjectShortName">next_ret_state</obj_property>
    </wvobject>
-   <wvobject fp_name="/lcd_driver_tb/uut/init_done" type="logic" db_ref_id="1">
-      <obj_property name="ElementShortName">init_done</obj_property>
-      <obj_property name="ObjectShortName">init_done</obj_property>
-   </wvobject>
    <wvobject fp_name="/lcd_driver_tb/uut/cur_counter" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">cur_counter[20:0]</obj_property>
       <obj_property name="ObjectShortName">cur_counter[20:0]</obj_property>

spi_driver.vhd

@@ -1,92 +1,80 @@
 ----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer: 
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
--- 
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    12:51:31 05/17/2016 
--- Design Name: 
--- Module Name:    spi_driver - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity spi_driver is
-	Generic (clk_freq: natural:= 50000000;
+   Generic (clk_freq: natural:= 50000000;           -- Clock-Frequency in Hz
-             adc_res: natural:=12);
+            adc_res: natural:=12);                  -- Number of bits the DAC has
-    Port ( clk : in  STD_LOGIC;
+    Port ( clk : in  STD_LOGIC;                     -- Clock input
-			  rst: in STD_LOGIC;
+           rst: in STD_LOGIC;                       -- High active, async reset
-           val : in  unsigned (adc_res-1 downto 0);
+           val : in  unsigned (adc_res-1 downto 0); -- DAC Value to write out 
-           sck : out  STD_LOGIC;
+           sck : out  STD_LOGIC;                    -- SPI SCK Signal (Clock)
-           cs : out  STD_LOGIC;
+           cs : out  STD_LOGIC;                     -- SPI CS Signal (Chip Select)
-           mosi : out  STD_LOGIC);
+           mosi : out  STD_LOGIC);                  -- SPI MOSI Signal (Master Out Slave in)
 end spi_driver;
 
 architecture Behavioral of spi_driver is
-	type states is(S_IDLE, S_WORK);
+   type states is(S_IDLE, S_WORK); -- FSM: Idle and Work State
-	signal state_reg, state_next: states := S_IDLE;
+   signal state_reg, state_next: states := S_IDLE; -- Current and next state register
-	signal counter_reg, counter_next: unsigned(5 downto 0) := (others => '0'); 
+   signal counter_reg, counter_next: unsigned(5 downto 0) := (others => '0'); -- Counter for the bit nr
-	signal shift_reg, shift_next: unsigned(19 downto 0):= (others => '0'); 
+   signal shift_reg, shift_next: unsigned(19 downto 0):= (others => '0'); -- Shift reg for the ouput
 begin
-	REGS: process (clk, rst) is
+   -- State register process (combinational)
-	begin                                   -- process start
+   REGS: process (clk, rst) is
-	  if rst = '1' then                 -- asynchronous reset (active high)
+   begin -- process start
-			state_reg <= S_IDLE;
+     if rst = '1' then  -- asynchronous reset (active high)
-			counter_reg <= to_unsigned(0,counter_reg'length);
+         state_reg <= S_IDLE;
-			shift_reg <= to_unsigned(0,shift_reg'length);
+         counter_reg <= to_unsigned(0,counter_reg'length);
-	  elsif rising_edge(clk) then         -- rising clock edge
+         shift_reg <= to_unsigned(0,shift_reg'length);
-			state_reg <= state_next;
+     elsif rising_edge(clk) then -- rising clock edge
-			counter_reg <= counter_next;
+         state_reg <= state_next;
-			shift_reg <= shift_next;
+         counter_reg <= counter_next;
-	  end if;
+         shift_reg <= shift_next;
-	end process REGS;
+     end if;
+   end process REGS;
 
-	mosi <= shift_reg(shift_reg'high) when state_reg=S_WORK else '0';
+   mosi <= shift_reg(shift_reg'high) when state_reg=S_WORK else '0'; -- Mosi: Highest value of shift reg when in Work state, otherwise 0
-	sck <= '1' when state_reg=S_WORK and counter_reg(0)='1' else '0';
+   sck <= '1' when state_reg=S_WORK and counter_reg(0)='1' else '0'; -- Sck: High when in work state and lowest bit 1 (shift will be performed when lowest bit = 0)
-	cs <= '1' when state_reg =S_IDLE else '0';
+   cs <= '0' when state_reg =S_WORK else '1'; -- Cs (low active): Low when in state work
 
-	NSL: process (state_reg, counter_reg, shift_reg, val) is
+   -- Next State logic process (combinational)
-	begin   
+   NSL: process (state_reg, counter_reg, shift_reg, val) is
-		state_next <= state_reg;
+   begin   
-		counter_next <= counter_reg;
+      state_next <= state_reg;
-		shift_next <= shift_reg;
+      counter_next <= counter_reg;
-		case state_reg is -- switch on current state
+      shift_next <= shift_reg;
-			when S_IDLE => -- currently in idle state
+      
-				state_next <= S_WORK;
+      case state_reg is -- switch on current state
-				counter_next <= to_unsigned(0,counter_reg'length);
+         when S_IDLE => -- currently in idle state
-				
+            state_next <= S_WORK;
-				shift_next(19 downto 16) <= "0011";  --Command: Write to and Update (Power Up) 
+            counter_next <= to_unsigned(0,counter_reg'length);
-				shift_next(15 downto 12) <= "0000";  --Adress: DAC0
+            
-				shift_next(11 downto 0) <= val; -- DAC Value (12bit)
+            -- Initialize shift reg
-				--shift_next(0 downto -3) <= "XXXX"; -- 4x don't care
+            shift_next(19 downto 16) <= "0011";  -- Command: Write to and Update (Power Up) 
-				
+            shift_next(15 downto 12) <= "0000";  -- Adress: DAC0
-			when S_WORK => -- currently in work state
+            shift_next(11 downto 0) <= val;      -- DAC Value (12bit)
-				if(counter_reg = 24*2 -1) then
+            --shift_next(0 downto -3) <= "XXXX"; -- 4x don't care
-					state_next <= S_IDLE;
+            
-				else
+         when S_WORK => -- currently in work state
-					counter_next<= counter_reg + 1;
+            if(counter_reg = 24*2 -1) then -- all bits sent
-				end if;
+               state_next <= S_IDLE; -- return to idle state
-				if(counter_reg(0)='1') then
+            else -- not all bits sent
-					shift_next <= shift_left(shift_reg,1);
+               counter_next<= counter_reg + 1; -- increase bit counter
-				end if;
+            end if;
-			when others => null; -- do nothing, if we are in a different state
+            if(counter_reg(0)='1') then -- peform shift when lowest bit = 1, shift will be performed when bit = 0
-		end case;	
+               shift_next <= shift_left(shift_reg,1);
-	end process NSL;
+            end if;
+         when others => null; -- do nothing, if we are in a different state
+      end case;   
+   end process NSL;
 
 end Behavioral;
 

spi_driver_tb.vhd

@@ -1,35 +1,13 @@
---------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer:
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
---
+-- Authors:        Aaron Schmocker & Timo Lang
--- Create Date:   15:38:41 05/17/2016
+-- License:        GPL v3
--- Design Name:   
+-- Create Date:    15:38:41 05/17/2016
--- Module Name:   /home/timo/vhdl-yasg/spi_driver_tb.vhd
+----------------------------------------------------------------------------------
--- Project Name:  yasg
+
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: spi_driver
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 USE ieee.numeric_std.ALL;
  
 ENTITY spi_driver_tb IS
@@ -56,7 +34,7 @@ ARCHITECTURE behavior OF spi_driver_tb IS
    signal rst : std_logic := '0';
    signal val : unsigned(11 downto 0) := (others => '0');
 
- 	--Outputs
+    --Outputs
    signal sck : std_logic;
    signal cs : std_logic;
    signal mosi : std_logic;
@@ -66,7 +44,7 @@ ARCHITECTURE behavior OF spi_driver_tb IS
  
 BEGIN
  
-	-- Instantiate the Unit Under Test (UUT)
+   -- Instantiate the Unit Under Test (UUT)
    uut: spi_driver PORT MAP (
           clk => clk,
           rst => rst,
@@ -79,36 +57,36 @@ BEGIN
    -- Clock process definitions
    clk_process :process
    begin
-		clk <= '0';
+      clk <= '0';
-		wait for clk_period/2;
+      wait for clk_period/2;
-		clk <= '1';
+      clk <= '1';
-		wait for clk_period/2;
+      wait for clk_period/2;
    end process;
  
 
    -- Stimulus process
    stim_proc: process
-   begin		
+   begin      
       -- hold reset state for 100 ns.
-		rst <= '1';
+      rst <= '1';
-      wait for 100 ns;	
+      wait for 100 ns;   
-		rst <= '0';
+      rst <= '0';
       wait for clk_period*10;
-		
+      
-		val <= to_unsigned(0,12);
+      val <= to_unsigned(0,12);
-		wait for clk_period*64;
+      wait for clk_period*64;
-		
+      
-		val <= to_unsigned(7,12);
+      val <= to_unsigned(7,12);
-		wait for clk_period*64;
+      wait for clk_period*64;
-		
+      
-		val <= to_unsigned(31,12);
+      val <= to_unsigned(31,12);
-		wait for clk_period*64;
+      wait for clk_period*64;
-		
+      
-		val <= to_unsigned(128,12);
+      val <= to_unsigned(128,12);
-		wait for clk_period*64;
+      wait for clk_period*64;
-		
+      
-		val <= to_unsigned(512,12);
+      val <= to_unsigned(512,12);
-		wait for clk_period*64;
+      wait for clk_period*64;
 
       -- insert stimulus here 
 

toplevel.jhd

@@ -4,8 +4,8 @@ MODULE toplevel
 	SUBMODULE dds
 		INSTANCE XLXI_2
 	SUBMODULE controller
-		INSTANCE XLXI_90
+		INSTANCE XLXI_92
 	SUBMODULE rotary_dec
-		INSTANCE XLXI_43
+		INSTANCE XLXI_91
 	SUBMODULE lcd_driver
 		INSTANCE XLXI_88

toplevel.sch

@@ -17,8 +17,6 @@
         <signal name="J18_IO2" />
         <signal name="J18_IO3" />
         <signal name="J18_IO1" />
-        <signal name="ROT_A" />
-        <signal name="ROT_B" />
         <signal name="XLXN_79" />
         <signal name="LCD_busy" />
         <signal name="LCD_RS" />
@@ -37,7 +35,10 @@
         <signal name="FORM(0)" />
         <signal name="BTN_EAST" />
         <signal name="XLXN_77" />
+        <signal name="ROT_A" />
+        <signal name="ROT_B" />
         <signal name="ROT_CENTER" />
+        <signal name="XLXN_181" />
         <port polarity="Input" name="CLK_50MHZ" />
         <port polarity="Output" name="SPI_SCK" />
         <port polarity="Output" name="DAC_CS" />
@@ -46,8 +47,6 @@
         <port polarity="Output" name="J18_IO2" />
         <port polarity="Output" name="J18_IO3" />
         <port polarity="Output" name="J18_IO1" />
-        <port polarity="Input" name="ROT_A" />
-        <port polarity="Input" name="ROT_B" />
         <port polarity="Output" name="LCD_RS" />
         <port polarity="Output" name="LCD_E" />
         <port polarity="Output" name="LCD_DB(7:0)" />
@@ -57,6 +56,8 @@
         <port polarity="Input" name="SW0" />
         <port polarity="Input" name="SW1" />
         <port polarity="Input" name="BTN_EAST" />
+        <port polarity="Input" name="ROT_A" />
+        <port polarity="Input" name="ROT_B" />
         <port polarity="Input" name="ROT_CENTER" />
         <blockdef name="spi_driver">
             <timestamp>2016-5-20T8:33:2</timestamp>
@@ -122,13 +123,15 @@
             <line x2="0" y1="-288" y2="-288" x1="64" />
         </blockdef>
         <blockdef name="rotary_dec">
-            <timestamp>2016-6-10T10:5:37</timestamp>
+            <timestamp>2016-6-13T11:22:41</timestamp>
-            <rect width="256" x="64" y="-192" height="192" />
+            <rect width="256" x="64" y="-256" height="256" />
+            <line x2="0" y1="-224" y2="-224" x1="64" />
             <line x2="0" y1="-160" y2="-160" x1="64" />
             <line x2="0" y1="-96" y2="-96" x1="64" />
             <line x2="0" y1="-32" y2="-32" x1="64" />
             <line x2="384" y1="-32" y2="-32" x1="320" />
             <line x2="384" y1="-96" y2="-96" x1="320" />
+            <line x2="384" y1="-160" y2="-160" x1="320" />
         </blockdef>
         <blockdef name="lcd_driver">
             <timestamp>2016-6-6T19:34:31</timestamp>
@@ -175,13 +178,6 @@
             <blockpin signalname="CLK_50MHZ" name="I" />
             <blockpin signalname="J18_IO1" name="O" />
         </block>
-        <block symbolname="rotary_dec" name="XLXI_43">
-            <blockpin signalname="CLK_50MHZ" name="clk" />
-            <blockpin signalname="ROT_A" name="A" />
-            <blockpin signalname="ROT_B" name="B" />
-            <blockpin signalname="XLXN_79" name="ce" />
-            <blockpin signalname="XLXN_77" name="right" />
-        </block>
         <block symbolname="lcd_driver" name="XLXI_88">
             <blockpin signalname="CLK_50MHZ" name="clk" />
             <blockpin signalname="BTN_EAST" name="reset" />
@@ -215,7 +211,16 @@
             <blockpin signalname="SW0" name="I" />
             <blockpin signalname="LED0" name="O" />
         </block>
-        <block symbolname="controller" name="XLXI_90">
+        <block symbolname="rotary_dec" name="XLXI_91">
+            <blockpin signalname="CLK_50MHZ" name="clk" />
+            <blockpin signalname="ROT_A" name="A" />
+            <blockpin signalname="ROT_B" name="B" />
+            <blockpin signalname="ROT_CENTER" name="btn" />
+            <blockpin signalname="XLXN_79" name="enc_ce" />
+            <blockpin signalname="XLXN_77" name="enc_right" />
+            <blockpin signalname="XLXN_181" name="btn_deb" />
+        </block>
+        <block symbolname="controller" name="XLXI_92">
             <blockpin signalname="CLK_50MHZ" name="clk" />
             <blockpin signalname="BTN_EAST" name="rst" />
             <blockpin signalname="LCD_busy" name="lcd_busy" />
@@ -226,7 +231,7 @@
             <blockpin signalname="FREQ(16:0)" name="freq_out(16:0)" />
             <blockpin signalname="XLXN_77" name="enc_right" />
             <blockpin signalname="XLXN_79" name="enc_ce" />
-            <blockpin signalname="ROT_CENTER" name="enc_btn" />
+            <blockpin signalname="XLXN_181" name="enc_btn" />
         </block>
     </netlist>
     <sheet sheetnum="1" width="5440" height="3520">
@@ -288,20 +293,10 @@
         <branch name="J18_IO1">
             <wire x2="3888" y1="1632" y2="1632" x1="3856" />
         </branch>
-        <branch name="ROT_A">
-            <wire x2="1136" y1="1600" y2="1600" x1="1056" />
-        </branch>
-        <branch name="ROT_B">
-            <wire x2="1136" y1="1664" y2="1664" x1="1056" />
-        </branch>
-        <branch name="CLK_50MHZ">
-            <wire x2="1136" y1="1536" y2="1536" x1="1056" />
-        </branch>
         <branch name="XLXN_79">
-            <wire x2="1792" y1="1664" y2="1664" x1="1520" />
+            <wire x2="1776" y1="1664" y2="1664" x1="1520" />
+            <wire x2="1792" y1="1664" y2="1664" x1="1776" />
         </branch>
-        <instance x="1136" y="1696" name="XLXI_43" orien="R0">
-        </instance>
         <branch name="LCD_busy">
             <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1648" y="1024" type="branch" />
             <wire x2="784" y1="1024" y2="1728" x1="784" />
@@ -323,9 +318,6 @@
         <iomarker fontsize="28" x="3888" y="1632" name="J18_IO1" orien="R0" />
         <iomarker fontsize="28" x="4336" y="1808" name="J18_IO4" orien="R0" />
         <iomarker fontsize="28" x="3472" y="1632" name="CLK_50MHZ" orien="R180" />
-        <iomarker fontsize="28" x="1056" y="1600" name="ROT_A" orien="R180" />
-        <iomarker fontsize="28" x="1056" y="1664" name="ROT_B" orien="R180" />
-        <iomarker fontsize="28" x="1056" y="1536" name="CLK_50MHZ" orien="R180" />
         <instance x="2736" y="1456" name="XLXI_88" orien="R0">
         </instance>
         <iomarker fontsize="28" x="2656" y="1168" name="CLK_50MHZ" orien="R180" />
@@ -423,16 +415,37 @@
         <branch name="CLK_50MHZ">
             <wire x2="1792" y1="1408" y2="1408" x1="1776" />
         </branch>
-        <branch name="ROT_CENTER">
-            <wire x2="1792" y1="1536" y2="1536" x1="1760" />
-        </branch>
         <branch name="BTN_EAST">
             <wire x2="1792" y1="1472" y2="1472" x1="1760" />
         </branch>
-        <iomarker fontsize="28" x="1760" y="1536" name="ROT_CENTER" orien="R180" />
         <iomarker fontsize="28" x="1760" y="1472" name="BTN_EAST" orien="R180" />
         <iomarker fontsize="28" x="1776" y="1408" name="CLK_50MHZ" orien="R180" />
-        <instance x="1792" y="1824" name="XLXI_90" orien="R0">
+        <branch name="ROT_A">
+            <wire x2="1072" y1="1536" y2="1536" x1="1056" />
+            <wire x2="1136" y1="1536" y2="1536" x1="1072" />
+        </branch>
+        <branch name="ROT_B">
+            <wire x2="1072" y1="1600" y2="1600" x1="1056" />
+            <wire x2="1136" y1="1600" y2="1600" x1="1072" />
+        </branch>
+        <branch name="CLK_50MHZ">
+            <wire x2="1072" y1="1472" y2="1472" x1="1056" />
+            <wire x2="1136" y1="1472" y2="1472" x1="1072" />
+        </branch>
+        <iomarker fontsize="28" x="1056" y="1536" name="ROT_A" orien="R180" />
+        <iomarker fontsize="28" x="1056" y="1600" name="ROT_B" orien="R180" />
+        <iomarker fontsize="28" x="1056" y="1472" name="CLK_50MHZ" orien="R180" />
+        <iomarker fontsize="28" x="1104" y="1664" name="ROT_CENTER" orien="R180" />
+        <instance x="1792" y="1824" name="XLXI_92" orien="R0">
         </instance>
+        <branch name="ROT_CENTER">
+            <wire x2="1120" y1="1664" y2="1664" x1="1104" />
+            <wire x2="1136" y1="1664" y2="1664" x1="1120" />
+        </branch>
+        <instance x="1136" y="1696" name="XLXI_91" orien="R0">
+        </instance>
+        <branch name="XLXN_181">
+            <wire x2="1792" y1="1536" y2="1536" x1="1520" />
+        </branch>
     </sheet>
 </drawing>

yasg.xise

@@ -16,7 +16,7 @@
 
   <files>
     <file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
@@ -34,11 +34,11 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
     </file>
     <file xil_pn:name="spi_driver.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="spi_driver_tb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="48"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/>
@@ -59,16 +59,22 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/>
     </file>
+    <file xil_pn:name="rotary_tb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/>
+    </file>
     <file xil_pn:name="controller_tb.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="143"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="80"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="80"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="80"/>
     </file>
   </files>
 
@@ -84,8 +90,8 @@
     <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spi_driver_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/lcd_driver_tb" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spi_driver_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.lcd_driver_tb" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -95,7 +101,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|spi_driver_tb|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|lcd_driver_tb|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>