78 lines
1.7 KiB
VHDL
78 lines
1.7 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project: YASG (Yet another signal generator)
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-- Project Page: https://github.com/id101010/vhdl-yasg/
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-- Authors: Aaron Schmocker & Timo Lang
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-- License: GPL v3
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-- Create Date: 13:41:21 06/19/2016
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY rotary_tb IS
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END rotary_tb;
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ARCHITECTURE behavior OF rotary_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT rotary_dec
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PORT(
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clk : IN std_logic;
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A : IN std_logic;
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B : IN std_logic;
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btn : IN std_logic;
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btn_deb : OUT std_logic;
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enc_right : OUT std_logic;
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enc_ce : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal A : std_logic := '0';
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signal B : std_logic := '0';
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signal btn : std_logic := '0';
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--Outputs
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signal btn_deb : std_logic;
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signal enc_right : std_logic;
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signal enc_ce : std_logic;
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: rotary_dec PORT MAP (
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clk => clk,
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A => A,
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B => B,
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btn => btn,
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btn_deb => btn_deb,
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enc_right => enc_right,
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enc_ce => enc_ce
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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wait;
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end process;
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END;
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