aaron/vhdl-yasg
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Improved lcd tb & screenshots

Browse Source
This commit is contained in:
id101010
2016-06-19 22:47:11 +02:00
parent 785fd243ea
commit fce08f5e1d
11 changed files with 19 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lcd_driver_tb.vhd
View File

@@ -37,7 +37,6 @@ ARCHITECTURE behavior OF lcd_driver_tb IS
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal new_character : std_logic := '0';
signal new_pos : std_logic := '0';
signal auto_incr_cursor : std_logic := '0';
--Outputs
signal lcd_db : std_logic_vector(7 downto 0);
@@ -90,6 +89,7 @@ BEGIN
new_pos <= '0';
wait until busy = '0';
wait for 10ms;
-- test sending character
data <= "10101010";
@@ -97,7 +97,9 @@ BEGIN
new_pos <= '1';
wait until busy = '0';
wait for 10ms;
-- Reset
data <= "00000000";
new_character <= '0';
new_pos <= '0';

BIN
screenshots/LCDTB1.png
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 15 KiB

BIN
screenshots/LCDTB2.png
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 14 KiB

BIN
screenshots/LCDTB3.png
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 44 KiB

BIN
screenshots/LCDTB4.png
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 43 KiB

BIN
screenshots/LCDTB5.png
View File

Binary file not shown.
Side by Side

Before

Width:  |  Height:  |  Size: 40 KiB

BIN
screenshots/LCD_TB_INIT1.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 44 KiB

BIN
screenshots/LCD_TB_INIT2.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 42 KiB

BIN
screenshots/LCD_TB_SEND.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 40 KiB

16
simulate_display_init.wcfg
View File

@@ -20,6 +20,14 @@
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/uut/busy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">busy</obj_property>
<obj_property name="ObjectShortName">busy</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/lcd_db" type="array" db_ref_id="1">
<obj_property name="ElementShortName">lcd_db[7:0]</obj_property>
<obj_property name="ObjectShortName">lcd_db[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[7:0]</obj_property>
<obj_property name="ObjectShortName">data[7:0]</obj_property>
@@ -32,14 +40,6 @@
<obj_property name="ElementShortName">new_pos</obj_property>
<obj_property name="ObjectShortName">new_pos</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/auto_incr_cursor" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">auto_incr_cursor</obj_property>
<obj_property name="ObjectShortName">auto_incr_cursor</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/lcd_db" type="array" db_ref_id="1">
<obj_property name="ElementShortName">lcd_db[7:0]</obj_property>
<obj_property name="ObjectShortName">lcd_db[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/uut/lcd_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">lcd_en</obj_property>
<obj_property name="ObjectShortName">lcd_en</obj_property>

16
yasg.xise
View File

@@ -16,19 +16,19 @@
<files>
<file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
@@ -59,7 +59,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/>
@@ -90,8 +90,8 @@
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/dds_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.dds_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/lcd_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.lcd_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -101,7 +101,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|dds_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|lcd_driver_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>