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Merge branch 'master' of github.com:id101010/vhdl-yasg

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id101010
2016-06-19 15:08:10 +02:00
parent aa632f5ac2 78ea176aac
commit 657a3e96a2
34 changed files with 490 additions and 660 deletions
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491
controller.vhd
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@@ -1,283 +1,264 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 18:47:36 05/23/2016
-- Design Name:
-- Module Name: controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity controller is
Port ( clk : in STD_LOGIC;
rst: in STD_LOGIC;
enc_right : in STD_LOGIC;
enc_ce : in STD_LOGIC;
enc_btn: in STD_LOGIC;
form : in unsigned(1 downto 0);
lcd_busy: in STD_LOGIC;
lcd_data: out unsigned(7 downto 0);
lcd_newchar: out STD_LOGIC;
lcd_newpos : out STD_LOGIC;
freq_out : out unsigned (16 downto 0));
Port ( clk : in STD_LOGIC; -- Clock Input
rst: in STD_LOGIC; -- High active, async reset
enc_right : in STD_LOGIC; -- Encoder Input: 1= Direction Right, 0 = Direction Left
enc_ce : in STD_LOGIC; -- Encoder Input: Clock Enable for Signal above
enc_btn: in STD_LOGIC; -- Encoder Input: Debounced Button (High active)
form : in unsigned(1 downto 0); -- Form selection (mapping see dds.vhd)
lcd_busy: in STD_LOGIC; -- LCD Feedback: Busy Signal: 1= LCD is currently busy
lcd_data: out unsigned(7 downto 0); -- LCD Output: Data output
lcd_newchar: out STD_LOGIC; -- LCD Output: Send a new character to the lcd
lcd_newpos : out STD_LOGIC; -- LCD Output: Send a new position/adress to the lcd
freq_out : out unsigned (16 downto 0)); -- Frequency Ouput (Treshould in Hz)
end controller;
architecture Behavioral of controller is
type states is(S_WAIT,
S_FORM_PREF, -- prints the form prefix ("Form:")
S_FREQ_PREF, -- frequenz prefix ("Freq: 00000 Hz")
S_FORM_CONT, -- form content ("Rechteck, Sinus...")
S_FREQ_CONT, -- frequenz content ("-----")
S_IDLE );
signal state_reg, state_next : states := S_WAIT;
signal ret_state_reg, ret_state_next: states := S_FORM_PREF;
type states is(S_WAIT,
S_FORM_PREF, -- prints the form prefix ("Form:")
S_FREQ_PREF, -- frequenz prefix ("Freq: 00000 Hz")
S_FORM_CONT, -- form content ("Rechteck, Sinus...")
S_FREQ_CONT, -- frequenz content ("-----")
S_IDLE );
signal state_reg, state_next : states := S_WAIT;
signal ret_state_reg, ret_state_next: states := S_FORM_PREF;
----- Edge detection registers -----
signal btn_old_reg, btn_old_next : std_logic := '0';
signal enc_old_reg, enc_old_next: std_logic :='0';
signal busy_old_reg, busy_old_next : std_logic := '0';
signal form_old_reg, form_old_next : unsigned (1 downto 0) := (others => '0');
--digitnr which is currently edited 0-4
signal digpos_reg, digpos_next : unsigned(2 downto 0) := (others => '0');
signal charcnt_reg, charcnt_next : unsigned(3 downto 0) := (others => '0');
-- array 5x 4bit(0-9)
type storage_digit is array (0 to 7) of unsigned (3 downto 0);
signal digit_reg, digit_next : storage_digit := (others => (others => '0'));
signal btn_old_reg, btn_old_next : std_logic := '0';
signal enc_old_reg, enc_old_next: std_logic :='0';
signal busy_old_reg, busy_old_next : std_logic := '0';
signal form_old_reg, form_old_next : unsigned (1 downto 0) := (others => '0');
--digitnr which is currently edited 0-4
signal digpos_reg, digpos_next : unsigned(2 downto 0) := (others => '0');
signal charcnt_reg, charcnt_next : unsigned(3 downto 0) := (others => '0');
-- array 5x 4bit(0-9)
type storage_digit is array (0 to 7) of unsigned (3 downto 0);
signal digit_reg, digit_next : storage_digit := (others => (others => '0'));
signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0';
signal lcd_newpos_reg,lcd_newpos_next : std_logic := '0';
signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0');
signal freq_out_reg, freq_out_next : unsigned (16 downto 0) := (others => '0');
----------------Constants---------------------------------
type character_array_short is array (0 to 7) of character;
constant str_form_pref : character_array_short := ( 'F', 'o', 'r','m',':', others => ' ' );
type character_array_long is array (0 to 15) of character;
constant str_freq_pref : character_array_long := ( 'F', 'r', 'e','q',':',' ','0','0','0','0','0',' ','H','z', others => ' ' );
type character_form_array is array (0 to 3, 0 to 7) of character;
constant str_form : character_form_array := (
('S','q','u','a','r','e',' ',' '),
('S','a','w','t','o','o','t','h'),
('T','r','i','a','n','g','l','e'),
('S','i','n','e',' ',' ',' ',' ')
);
signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0';
signal lcd_newpos_reg,lcd_newpos_next : std_logic := '0';
signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0');
signal freq_out_reg, freq_out_next : unsigned (16 downto 0) := (others => '0');
----------------Constants---------------------------------
type character_array_short is array (0 to 7) of character;
constant str_form_pref : character_array_short := ( 'F', 'o', 'r','m',':', others => ' ' );
type character_array_long is array (0 to 15) of character;
constant str_freq_pref : character_array_long := ( 'F', 'r', 'e','q',':',' ','0','0','0','0','0',' ','H','z', others => ' ' );
type character_form_array is array (0 to 3, 0 to 7) of character;
constant str_form : character_form_array := (
('S','q','u','a','r','e',' ',' '),
('S','a','w','t','o','o','t','h'),
('T','r','i','a','n','g','l','e'),
('S','i','n','e',' ',' ',' ',' ')
);
begin
proc1: process(clk,rst)
begin
if(rst='1') then
digpos_reg <= (others => '0');
digit_reg <= (others => (others => '0'));
btn_old_reg <= '0';
enc_old_reg <='0';
busy_old_reg <= '0';
form_old_reg <= "00";
charcnt_reg <= (others => '0');
lcd_newchar_reg <= '0';
lcd_newpos_reg <= '0';
lcd_data_reg <= (others => '0');
proc1: process(clk,rst)
begin
if(rst='1') then
digpos_reg <= (others => '0');
digit_reg <= (others => (others => '0'));
btn_old_reg <= '0';
enc_old_reg <='0';
busy_old_reg <= '0';
form_old_reg <= "00";
charcnt_reg <= (others => '0');
lcd_newchar_reg <= '0';
lcd_newpos_reg <= '0';
lcd_data_reg <= (others => '0');
freq_out_reg <=(others => '0');
state_reg <= S_WAIT;
ret_state_reg <= S_FORM_PREF;
elsif(rising_edge(clk)) then
digpos_reg <= digpos_next;
digit_reg <= digit_next;
btn_old_reg <= btn_old_next;
enc_old_reg <= enc_old_next;
busy_old_reg <= busy_old_next;
form_old_reg <= form_old_next;
charcnt_reg <= charcnt_next;
lcd_newchar_reg<= lcd_newchar_next;
lcd_newpos_reg<= lcd_newpos_next;
lcd_data_reg <= lcd_data_next;
freq_out_reg <=(others => '0');
state_reg <= S_WAIT;
ret_state_reg <= S_FORM_PREF;
elsif(rising_edge(clk)) then
digpos_reg <= digpos_next;
digit_reg <= digit_next;
btn_old_reg <= btn_old_next;
enc_old_reg <= enc_old_next;
busy_old_reg <= busy_old_next;
form_old_reg <= form_old_next;
charcnt_reg <= charcnt_next;
lcd_newchar_reg<= lcd_newchar_next;
lcd_newpos_reg<= lcd_newpos_next;
lcd_data_reg <= lcd_data_next;
freq_out_reg <= freq_out_next;
state_reg <= state_next;
ret_state_reg <= ret_state_next;
end if;
end process proc1;
freq_out_reg <= freq_out_next;
state_reg <= state_next;
ret_state_reg <= ret_state_next;
end if;
end process proc1;
freq_out <= freq_out_reg;
lcd_data <= lcd_data_reg;
lcd_newchar <= lcd_newchar_reg;
lcd_newpos <= lcd_newpos_reg;
NSL: process(digit_reg,enc_right,enc_ce,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, busy_old_reg, state_reg, ret_state_reg, enc_ce,enc_old_reg, form_old_reg, form)
begin
digit_next <= digit_reg;
digpos_next <= digpos_reg;
busy_old_next <= lcd_busy;
btn_old_next <= btn_old_reg;
enc_old_next <= enc_old_reg;
form_old_next <= form_old_reg;
freq_out <= freq_out_reg;
lcd_data <= lcd_data_reg;
lcd_newchar <= lcd_newchar_reg;
lcd_newpos <= lcd_newpos_reg;
NSL: process(digit_reg,enc_right,enc_ce,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, busy_old_reg, state_reg, ret_state_reg, enc_ce,enc_old_reg, form_old_reg, form)
begin
digit_next <= digit_reg;
digpos_next <= digpos_reg;
busy_old_next <= lcd_busy;
btn_old_next <= btn_old_reg;
enc_old_next <= enc_old_reg;
form_old_next <= form_old_reg;
charcnt_next <= charcnt_reg;
lcd_newchar_next <= '0';
lcd_newpos_next <= '0';
lcd_data_next <= lcd_data_reg;
charcnt_next <= charcnt_reg;
lcd_newchar_next <= '0';
lcd_newpos_next <= '0';
lcd_data_next <= lcd_data_reg;
state_next <= state_reg;
ret_state_next <= ret_state_reg;
-- The next statement produces two warnings which can be safely ignored:
-- xst:643 - The result of a <...>-bit multiplication is partially used...
freq_out_next <= resize(
resize(digit_reg(0), 4)
+ resize(digit_reg(1) ,4)* 10
+ resize(digit_reg(2) ,7)* 100
+ resize(digit_reg(3) ,10) * 1000
+ resize(digit_reg(4) ,14) * 10000
, 17);
case state_reg is
state_next <= state_reg;
ret_state_next <= ret_state_reg;
-- The next statement produces two warnings which can be safely ignored:
-- xst:643 - The result of a <...>-bit multiplication is partially used...
freq_out_next <= resize(
resize(digit_reg(0), 4)
+ resize(digit_reg(1) ,4)* 10
+ resize(digit_reg(2) ,7)* 100
+ resize(digit_reg(3) ,10) * 1000
+ resize(digit_reg(4) ,14) * 10000
, 17);
case state_reg is
when S_WAIT => -- switch on current state
if(lcd_busy = '0' and busy_old_reg ='1' ) then
state_next<= ret_state_reg;
end if;
when S_FORM_PREF =>
state_next <= S_WAIT;
if(charcnt_reg < 7 ) then
charcnt_next <= charcnt_reg + 1;
ret_state_next <= S_FORM_PREF;
lcd_data_next <= to_unsigned(character'pos(str_form_pref(to_integer(resize(charcnt_reg,3)))),8);
lcd_newchar_next <= '1';
else
charcnt_next <= (others => '0');
lcd_data_next <= x"40"; --Start adress for line 2
lcd_newpos_next <= '1';
ret_state_next <= S_FREQ_PREF;
end if;
when S_FREQ_PREF =>
if(charcnt_reg < 15 ) then
charcnt_next <= charcnt_reg + 1;
state_next <= S_WAIT;
ret_state_next <= S_FREQ_PREF;
lcd_data_next <= to_unsigned(character'pos(str_freq_pref(to_integer(charcnt_reg))),8);
lcd_newchar_next <= '1';
else
charcnt_next <= (others => '0');
state_next <= S_FORM_CONT;
end if;
when S_FORM_CONT =>
state_next <= S_WAIT;
ret_state_next <= S_FORM_CONT;
charcnt_next <= charcnt_reg + 1;
if(charcnt_reg < 1 ) then
lcd_data_next <= x"06"; --adress character 7 on line 1
lcd_newpos_next <= '1';
elsif(charcnt_reg < 9) then
lcd_data_next <= to_unsigned(character'pos(str_form(to_integer(form),to_integer(resize(charcnt_reg-1,3)))),8);
lcd_newchar_next <= '1';
else
charcnt_next <= (others => '0');
lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
lcd_newpos_next <= '1';
ret_state_next <= S_IDLE;
end if;
when S_FREQ_CONT =>
state_next <= S_WAIT;
if(charcnt_reg < 1 ) then
charcnt_next <= charcnt_reg + 1;
ret_state_next <= S_FREQ_CONT;
lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
lcd_newpos_next <= '1';
elsif(charcnt_reg = 1) then
charcnt_next <= charcnt_reg + 1;
ret_state_next <= S_FREQ_CONT;
lcd_data_next <= to_unsigned(character'pos('0'),8) + digit_reg(to_integer(digpos_reg));
lcd_newchar_next <= '1';
else
ret_state_next <= S_IDLE;
charcnt_next <= (others => '0');
lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
lcd_newpos_next <= '1';
end if;
when S_IDLE =>
btn_old_next <= enc_btn;
enc_old_next <= enc_ce;
form_old_next <= form;
if(lcd_busy = '0' and busy_old_reg ='1' ) then
state_next<= ret_state_reg;
end if;
when S_FORM_PREF =>
state_next <= S_WAIT;
if(charcnt_reg < 7 ) then
charcnt_next <= charcnt_reg + 1;
ret_state_next <= S_FORM_PREF;
lcd_data_next <= to_unsigned(character'pos(str_form_pref(to_integer(resize(charcnt_reg,3)))),8);
lcd_newchar_next <= '1';
else
charcnt_next <= (others => '0');
lcd_data_next <= x"40"; --Start adress for line 2
lcd_newpos_next <= '1';
ret_state_next <= S_FREQ_PREF;
end if;
when S_FREQ_PREF =>
if(charcnt_reg < 15 ) then
charcnt_next <= charcnt_reg + 1;
state_next <= S_WAIT;
ret_state_next <= S_FREQ_PREF;
lcd_data_next <= to_unsigned(character'pos(str_freq_pref(to_integer(charcnt_reg))),8);
lcd_newchar_next <= '1';
else
charcnt_next <= (others => '0');
state_next <= S_FORM_CONT;
end if;
when S_FORM_CONT =>
state_next <= S_WAIT;
ret_state_next <= S_FORM_CONT;
charcnt_next <= charcnt_reg + 1;
if(charcnt_reg < 1 ) then
lcd_data_next <= x"06"; --adress character 7 on line 1
lcd_newpos_next <= '1';
elsif(charcnt_reg < 9) then
lcd_data_next <= to_unsigned(character'pos(str_form(to_integer(form),to_integer(resize(charcnt_reg-1,3)))),8);
lcd_newchar_next <= '1';
else
charcnt_next <= (others => '0');
lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
lcd_newpos_next <= '1';
ret_state_next <= S_IDLE;
end if;
when S_FREQ_CONT =>
state_next <= S_WAIT;
if(charcnt_reg < 1 ) then
charcnt_next <= charcnt_reg + 1;
ret_state_next <= S_FREQ_CONT;
lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
lcd_newpos_next <= '1';
elsif(charcnt_reg = 1) then
charcnt_next <= charcnt_reg + 1;
ret_state_next <= S_FREQ_CONT;
lcd_data_next <= to_unsigned(character'pos('0'),8) + digit_reg(to_integer(digpos_reg));
lcd_newchar_next <= '1';
else
ret_state_next <= S_IDLE;
charcnt_next <= (others => '0');
lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
lcd_newpos_next <= '1';
end if;
when S_IDLE =>
btn_old_next <= enc_btn;
enc_old_next <= enc_ce;
form_old_next <= form;
if(form /= form_old_reg) then
state_next <= S_FORM_CONT;
elsif(enc_ce='1' and enc_old_reg ='0') then
if(enc_right='1') then
if(digit_reg(to_integer(digpos_reg)) = to_unsigned(9,4)) then
digit_next(to_integer(digpos_reg)) <= to_unsigned(0,4);
else
digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) + 1;
end if;
else
if(digit_reg(to_integer(digpos_reg)) = to_unsigned(0,4)) then
digit_next(to_integer(digpos_reg)) <= to_unsigned(9,4);
else
digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) -1;
end if;
end if;
state_next <= S_FREQ_CONT;
elsif(enc_btn ='1' and btn_old_reg='0') then
if(digpos_reg = to_unsigned(4,3)) then
digpos_next <= to_unsigned(0,3);
else
digpos_next <= digpos_reg + 1;
end if;
state_next <= S_FREQ_CONT;
end if;
if(form /= form_old_reg) then
state_next <= S_FORM_CONT;
elsif(enc_ce='1' and enc_old_reg ='0') then
if(enc_right='1') then
if(digit_reg(to_integer(digpos_reg)) = to_unsigned(9,4)) then
digit_next(to_integer(digpos_reg)) <= to_unsigned(0,4);
else
digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) + 1;
end if;
else
if(digit_reg(to_integer(digpos_reg)) = to_unsigned(0,4)) then
digit_next(to_integer(digpos_reg)) <= to_unsigned(9,4);
else
digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) -1;
end if;
end if;
state_next <= S_FREQ_CONT;
elsif(enc_btn ='1' and btn_old_reg='0') then
if(digpos_reg = to_unsigned(4,3)) then
digpos_next <= to_unsigned(0,3);
else
digpos_next <= digpos_reg + 1;
end if;
state_next <= S_FREQ_CONT;
end if;
when others => null; -- do nothing, if we are in a different state
end case;
end process NSL;
end case;
end process NSL;
end Behavioral;

58
controller_tb.vhd
View File

@@ -1,35 +1,13 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:08:51 06/06/2016
-- Design Name:
-- Module Name: /home/timo/workspace/vhdl-yasg/controller_tb.vhd
-- Project Name: yasg
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 20:08:51 06/06/2016
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY controller_tb IS
@@ -64,7 +42,7 @@ ARCHITECTURE behavior OF controller_tb IS
signal enc_err : std_logic := '0';
signal lcd_busy : std_logic := '0';
--Outputs
--Outputs
signal lcd_data : unsigned(7 downto 0);
signal lcd_newchar : std_logic;
signal freq_out : unsigned(16 downto 0);
@@ -74,7 +52,7 @@ ARCHITECTURE behavior OF controller_tb IS
BEGIN
-- Instantiate the Unit Under Test (UUT)
-- Instantiate the Unit Under Test (UUT)
uut: controller PORT MAP (
clk => clk,
rst => rst,
@@ -91,24 +69,24 @@ BEGIN
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for 100 ns;
wait for clk_period*10;
rst<= '0';
lcd_busy <= '0';
rst<= '0';
lcd_busy <= '0';
-- insert stimulus here

81
dds.vhd
View File

@@ -1,22 +1,11 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 11:09:53 05/16/2016
-- Design Name:
-- Module Name: dds - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
@@ -24,15 +13,15 @@ use IEEE.MATH_REAL.ALL;
use work.helpers.all;
entity dds is
Generic (clk_freq: natural:= 50000000;
freq_res: natural:=17; -- width of frequency input (log2(max_freq))
adc_res: natural:=12; -- width of the ouput signal (=adc resolution)
acc_res: natural:=32; -- width of the phase accumulator
phase_res: natural:=10); -- effective phase resolution for sin lookup table
Port ( clk : in STD_LOGIC;
freq : in unsigned (freq_res-1 downto 0);
form : in unsigned (1 downto 0);
amp : out unsigned (adc_res-1 downto 0));
Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz
freq_res: natural:=17; -- width of frequency input (log2(max_freq))
adc_res: natural:=12; -- width of the ouput signal (=adc resolution)
acc_res: natural:=32; -- width of the phase accumulator
phase_res: natural:=10); -- effective phase resolution for sin lookup table
Port ( clk : in STD_LOGIC; -- Clock input
freq : in unsigned (freq_res-1 downto 0); -- Frequenzy input (treshould in Hz)
form : in unsigned (1 downto 0); -- Form selection (00=Rectancle, 01=Sawtooth, 10=Triangle, 11=Sine)
amp : out unsigned (adc_res-1 downto 0)); -- Signal Output (Amplitude)
end dds;
architecture Behavioral of dds is
@@ -41,15 +30,15 @@ architecture Behavioral of dds is
signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0);
type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0);
--type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
--type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
function gen_sin_wave return storage is
variable temp : storage;
begin
forLoop: for i in 0 to temp'high loop
temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1);
--temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1) + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);
end loop;
--temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1) + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);
end loop;
return temp;
end function gen_sin_wave;
constant sin_wave : storage := gen_sin_wave;
@@ -57,34 +46,34 @@ architecture Behavioral of dds is
begin
-- m = fout*(2^n)/fclk = fout*((2^n)*(2^k)/fclk)/(2^k) with k=ceil(log2(fclk)), n=acc_res
m <= resize( (resize(freq,64)
*
(shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq))
/to_unsigned(2**log2_int(clk_freq),64),acc_res);
m <= resize( (resize(freq,64)
*
(shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq))
/to_unsigned(2**log2_int(clk_freq),64),acc_res);
amp_rect <= to_unsigned(0,adc_res) when idx(acc_res-1)='0' else
to_unsigned((2**adc_res)-1,adc_res);
amp_saw <= idx(acc_res -1 downto acc_res - adc_res);
amp_tria <= idx(acc_res -2 downto acc_res - adc_res) & "0"
amp_tria <= idx(acc_res -2 downto acc_res - adc_res) & "0"
when idx(acc_res-1)='0' else
((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res) & "0");
((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res) & "0");
idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
--amp_sin <= sin_wave(to_integer(idx_phase));
amp_sin <= to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else
idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
--amp_sin <= sin_wave(to_integer(idx_phase));
amp_sin <= to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="01" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="10" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0)));
amp <= to_unsigned(0,adc_res) when freq = to_unsigned(0,freq_res) else
amp_rect when form = "00" else
amp <= to_unsigned(0,adc_res) when freq = to_unsigned(0,freq_res) else
amp_rect when form = "00" else
amp_saw when form ="01" else
amp_tria when form = "10" else
amp_sin;

49
dds_tb.vhd
View File

@@ -1,30 +1,11 @@
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 11:35:57 05/16/2016
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:35:57 05/16/2016
-- Design Name:
-- Module Name: /home/timo/vhdl-yasg/dds_tb.vhd
-- Project Name: yasg
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dds
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
@@ -51,7 +32,7 @@ ARCHITECTURE behavior OF dds_tb IS
signal freq : unsigned(16 downto 0) := (others => '0');
signal form : unsigned(1 downto 0) := (others => '0');
--Outputs
--Outputs
signal amp : unsigned(11 downto 0);
-- Clock period definitions
@@ -59,7 +40,7 @@ ARCHITECTURE behavior OF dds_tb IS
BEGIN
-- Instantiate the Unit Under Test (UUT)
-- Instantiate the Unit Under Test (UUT)
uut: dds PORT MAP (
clk => clk,
freq => freq,
@@ -70,18 +51,18 @@ BEGIN
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for 100 ns;

32
helpers.vhd
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@@ -1,3 +1,10 @@
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 12:59:01 05/16/2016
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -6,11 +13,9 @@ use IEEE.NUMERIC_STD.ALL;
package helpers is
--helper function to calculate the log2 (truncated) of a integer
function log2_int(n:natural) return natural;
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
end helpers;
package body helpers is
function log2_int(n:natural) return natural is
begin
@@ -19,28 +24,5 @@ package body helpers is
end if;
return 1; --since we can no longer divide n, return 1
end log2_int;
--Source: http://vhdlguru.blogspot.ch/2010/03/vhdl-function-for-division-two-signed.html
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
variable a1 : unsigned(a'length-1 downto 0):=a;
variable b1 : unsigned(b'length-1 downto 0):=b;
variable p1 : unsigned(b'length downto 0):= (others => '0');
variable i : integer:=0;
begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;
end helpers;

8
io.ucf
View File

@@ -1,3 +1,11 @@
#---------------------------------------------------------------------------------
#- Project: YASG (Yet another signal generator)
#- Project Page: https://github.com/id101010/vhdl-yasg/
#- Authors: Aaron Schmocker & Timo Lang
#- License: GPL v3
#- Create Date: 16:23:12 05/20/2016
#---------------------------------------------------------------------------------
NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;

4
iseconfig/filter.filter
View File

@@ -6,8 +6,8 @@
<filters xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation='filter.xsd'>
<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_8</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
<filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_6</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
<filter task="xst" file="Xst" num="643" type="warning"><arg index="1" match_type="wildcard">/home/timo/workspace/vhdl-yasg/controller.vhd</arg><arg index="2" match_type="wildcard">169</arg><arg index="3" match_type="wildcard">*</arg><arg index="4" match_type="wildcard">*</arg><arg index="5" match_type="wildcard">17</arg></filter>
<filter task="xst" file="Xst" num="643" type="warning"><arg index="1">/home/timo/workspace/vhdl-yasg/controller.vhd</arg><arg index="2" match_type="wildcard">*</arg><arg index="3" match_type="wildcard">*</arg><arg index="4" match_type="wildcard">*</arg><arg index="5">17</arg></filter>
<filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_7</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_reg_0</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_reg_0</arg><arg index="2" match_type="wildcard">*</arg><arg index="3">controller</arg></filter>
<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">lcd_data_reg_7</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
</filters>

64
lcd_driver.vhd
View File

@@ -1,45 +1,15 @@
----------------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Company: Berner Fachhochschule
-- Engineer: Aaron Schmocker
--
-- Create Date: 19:29:54 05/09/2016
-- Design Name:
-- Module Name: lcddriver - Behavioral
-- Project Name: yasg
-- Target Devices: Spartan-3am Board
-- Tool versions:
-- Description: This file is part of the yasg project
--
-- Dependencies:
--
-- Additional Comments:
--
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 19:29:54 05/09/2016
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd_driver is
generic ( NBITS : natural := 21; -- counter bit size
@@ -48,15 +18,15 @@ entity lcd_driver is
wait_between : natural := 37; -- wait 37us
wait_pause : natural := 1520); -- wait 1.52ms
Port ( clk : in STD_LOGIC; -- Systemclock (50MHz)
reset : in STD_LOGIC; -- Initialize display controller
data : in STD_LOGIC_VECTOR (7 downto 0); -- either one ascii char (8bit) or new cursor position (0-31)
Port ( clk : in STD_LOGIC; -- Clock Input
reset : in STD_LOGIC; -- High active, async reset
data : in STD_LOGIC_VECTOR (7 downto 0); -- either one ascii char (8bit) or new cursor position/adress
new_character : in STD_LOGIC; -- a new character is available on the data bus
new_pos : in STD_LOGIC; -- a new cursor position is available on the data bus
busy : out STD_LOGIC; -- 1 when sending stuff
lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd databus
lcd_en : out STD_LOGIC; -- lcd enable
lcd_rs : out STD_LOGIC); -- lcd register select
busy : out STD_LOGIC; -- output which signals that the driver/lcd is currently busy
lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd output: databus
lcd_en : out STD_LOGIC; -- lcd output: enable
lcd_rs : out STD_LOGIC); -- lcd output: register select
end lcd_driver;
architecture Behavioral of lcd_driver is
@@ -215,15 +185,15 @@ begin
next_lcd_rs <= '0';
if(new_character = '1') then -- send data
next_ret_state <= DONE;
next_state <= WAITING1;
next_ret_state <= DONE;
next_state <= WAITING1;
next_lcd_rs <= '1';
next_counter <= (others => '0');
next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
next_lcd_db <= data;
elsif(new_pos = '1') then -- new address
next_state <= WAITING1;
next_ret_state <= DONE;
next_state <= WAITING1;
next_ret_state <= DONE;
next_lcd_db <= '1' & data(6 downto 0);
next_counter <= (others => '0');
next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);

53
lcd_driver_tb.vhd
View File

@@ -1,37 +1,14 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:11:41 05/16/2016
-- Design Name:
-- Module Name: /home/aaron/Dokumente/STUDIUM/SEM6/EloSys/EloSysDigital/Projekt/vhdl-yasg/lcd_driver_tb.vhd
-- Project Name: yasg
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: lcd_driver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 21:11:41 05/16/2016
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY lcd_driver_tb IS
END lcd_driver_tb;
@@ -60,7 +37,7 @@ ARCHITECTURE behavior OF lcd_driver_tb IS
signal new_pos : std_logic := '0';
signal auto_incr_cursor : std_logic := '0';
--Outputs
--Outputs
signal lcd_db : std_logic_vector(7 downto 0);
signal lcd_en : std_logic;
signal lcd_rw : std_logic;
@@ -71,7 +48,7 @@ ARCHITECTURE behavior OF lcd_driver_tb IS
BEGIN
-- Instantiate the Unit Under Test (UUT)
-- Instantiate the Unit Under Test (UUT)
uut: lcd_driver PORT MAP (
clk => clk,
reset => reset,
@@ -85,16 +62,16 @@ BEGIN
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
begin
reset <= '1';
wait for 100 ns; -- hold reset state for 100 ns.

88
rotary.vhd
View File

@@ -1,21 +1,23 @@
-----------------------------------------------------------------------------
--
-- Decoder für Drehgeber
--
-----------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 19:07:22 05/23/2016
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rotary_dec is
Port ( clk : in std_logic; -- Systemtakt
A : in std_logic; -- Spur A
B : in std_logic; -- Spur B
btn : in std_logic; -- Button Input
btn_deb : out std_logic; -- Button entprellt
enc_right: out std_logic; -- Zaehlrichtung
enc_ce : out std_logic); -- Clock Enable
Port ( clk : in std_logic; -- Clock Input
A : in std_logic; -- Signal A
B : in std_logic; -- Signal B
btn : in std_logic; -- Button Input
btn_deb : out std_logic; -- Button Output Debonced
enc_right: out std_logic; -- Direction Output: 1=right
enc_ce : out std_logic); -- Clock Enable Output for signal above
end rotary_dec;
@@ -25,8 +27,8 @@ signal a_old, b_old: std_logic := '0';
signal a_debounced_reg, a_debounced_next, b_debounced_reg, b_debounced_next : std_logic := '0';
signal btn_reg, btn_next: std_logic :='0';
signal counter_a_reg, counter_a_next,
counter_b_reg, counter_b_next,
counter_btn_reg, counter_btn_next: unsigned(23 downto 0) := (others => '0');
counter_b_reg, counter_b_next,
counter_btn_reg, counter_btn_next: unsigned(23 downto 0) := (others => '0');
constant count_max: unsigned(23 downto 0) := to_unsigned(500000,24); --10ms
begin
@@ -35,13 +37,13 @@ process(clk)
begin
if rising_edge(clk) then
counter_a_reg <= counter_a_next;
counter_b_reg <= counter_b_next;
counter_btn_reg <= counter_btn_next;
a_debounced_reg <= a_debounced_next;
b_debounced_reg <= b_debounced_next;
counter_b_reg <= counter_b_next;
counter_btn_reg <= counter_btn_next;
a_debounced_reg <= a_debounced_next;
b_debounced_reg <= b_debounced_next;
a_old <= a_debounced_reg;
b_old <= b_debounced_reg;
btn_reg <= btn_next;
btn_reg <= btn_next;
end if;
end process;
@@ -50,30 +52,30 @@ btn_deb <= btn_reg;
process(A,B, a_debounced_reg, b_debounced_reg, counter_a_reg, counter_b_reg, btn_reg, btn, counter_btn_reg)
begin
if(A /= a_debounced_reg and counter_a_reg > count_max) then
a_debounced_next <= A;
counter_a_next <= (others => '0');
else
a_debounced_next <= a_debounced_reg;
counter_a_next <= counter_a_reg + 1;
end if;
if(B /= b_debounced_reg and counter_b_reg > count_max) then
b_debounced_next <= B;
counter_b_next <= (others => '0');
else
b_debounced_next <= b_debounced_reg;
counter_b_next <= counter_b_reg + 1;
end if;
if(btn /= btn_reg and counter_btn_reg > count_max) then
btn_next <= btn;
counter_btn_next <= (others => '0');
else
btn_next <= btn_reg;
counter_btn_next <= counter_btn_reg + 1;
end if;
if(A /= a_debounced_reg and counter_a_reg > count_max) then
a_debounced_next <= A;
counter_a_next <= (others => '0');
else
a_debounced_next <= a_debounced_reg;
counter_a_next <= counter_a_reg + 1;
end if;
if(B /= b_debounced_reg and counter_b_reg > count_max) then
b_debounced_next <= B;
counter_b_next <= (others => '0');
else
b_debounced_next <= b_debounced_reg;
counter_b_next <= counter_b_reg + 1;
end if;
if(btn /= btn_reg and counter_btn_reg > count_max) then
btn_next <= btn;
counter_btn_next <= (others => '0');
else
btn_next <= btn_reg;
counter_btn_next <= counter_btn_reg + 1;
end if;
end process;

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134
spi_driver.vhd
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@@ -1,92 +1,76 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 12:51:31 05/17/2016
-- Design Name:
-- Module Name: spi_driver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_driver is
Generic (clk_freq: natural:= 50000000;
adc_res: natural:=12);
Port ( clk : in STD_LOGIC;
rst: in STD_LOGIC;
val : in unsigned (adc_res-1 downto 0);
sck : out STD_LOGIC;
cs : out STD_LOGIC;
mosi : out STD_LOGIC);
Generic (clk_freq: natural:= 50000000; -- Clock-Frequency in Hz
adc_res: natural:=12); -- Number of bits the DAC has
Port ( clk : in STD_LOGIC; -- Clock input
rst: in STD_LOGIC; -- High active, async reset
val : in unsigned (adc_res-1 downto 0); -- DAC Value to write out
sck : out STD_LOGIC; -- SPI SCK Signal (Clock)
cs : out STD_LOGIC; -- SPI CS Signal (Chip Select)
mosi : out STD_LOGIC); -- SPI MOSI Signal (Master Out Slave in)
end spi_driver;
architecture Behavioral of spi_driver is
type states is(S_IDLE, S_WORK);
signal state_reg, state_next: states := S_IDLE;
signal counter_reg, counter_next: unsigned(5 downto 0) := (others => '0');
signal shift_reg, shift_next: unsigned(19 downto 0):= (others => '0');
type states is(S_IDLE, S_WORK);
signal state_reg, state_next: states := S_IDLE;
signal counter_reg, counter_next: unsigned(5 downto 0) := (others => '0');
signal shift_reg, shift_next: unsigned(19 downto 0):= (others => '0');
begin
REGS: process (clk, rst) is
begin -- process start
if rst = '1' then -- asynchronous reset (active high)
state_reg <= S_IDLE;
counter_reg <= to_unsigned(0,counter_reg'length);
shift_reg <= to_unsigned(0,shift_reg'length);
elsif rising_edge(clk) then -- rising clock edge
state_reg <= state_next;
counter_reg <= counter_next;
shift_reg <= shift_next;
end if;
end process REGS;
REGS: process (clk, rst) is
begin -- process start
if rst = '1' then -- asynchronous reset (active high)
state_reg <= S_IDLE;
counter_reg <= to_unsigned(0,counter_reg'length);
shift_reg <= to_unsigned(0,shift_reg'length);
elsif rising_edge(clk) then -- rising clock edge
state_reg <= state_next;
counter_reg <= counter_next;
shift_reg <= shift_next;
end if;
end process REGS;
mosi <= shift_reg(shift_reg'high) when state_reg=S_WORK else '0';
sck <= '1' when state_reg=S_WORK and counter_reg(0)='1' else '0';
cs <= '1' when state_reg =S_IDLE else '0';
mosi <= shift_reg(shift_reg'high) when state_reg=S_WORK else '0';
sck <= '1' when state_reg=S_WORK and counter_reg(0)='1' else '0';
cs <= '1' when state_reg =S_IDLE else '0';
NSL: process (state_reg, counter_reg, shift_reg, val) is
begin
state_next <= state_reg;
counter_next <= counter_reg;
shift_next <= shift_reg;
case state_reg is -- switch on current state
when S_IDLE => -- currently in idle state
state_next <= S_WORK;
counter_next <= to_unsigned(0,counter_reg'length);
shift_next(19 downto 16) <= "0011"; --Command: Write to and Update (Power Up)
shift_next(15 downto 12) <= "0000"; --Adress: DAC0
shift_next(11 downto 0) <= val; -- DAC Value (12bit)
--shift_next(0 downto -3) <= "XXXX"; -- 4x don't care
when S_WORK => -- currently in work state
if(counter_reg = 24*2 -1) then
state_next <= S_IDLE;
else
counter_next<= counter_reg + 1;
end if;
if(counter_reg(0)='1') then
shift_next <= shift_left(shift_reg,1);
end if;
when others => null; -- do nothing, if we are in a different state
end case;
end process NSL;
NSL: process (state_reg, counter_reg, shift_reg, val) is
begin
state_next <= state_reg;
counter_next <= counter_reg;
shift_next <= shift_reg;
case state_reg is -- switch on current state
when S_IDLE => -- currently in idle state
state_next <= S_WORK;
counter_next <= to_unsigned(0,counter_reg'length);
shift_next(19 downto 16) <= "0011"; --Command: Write to and Update (Power Up)
shift_next(15 downto 12) <= "0000"; --Adress: DAC0
shift_next(11 downto 0) <= val; -- DAC Value (12bit)
--shift_next(0 downto -3) <= "XXXX"; -- 4x don't care
when S_WORK => -- currently in work state
if(counter_reg = 24*2 -1) then
state_next <= S_IDLE;
else
counter_next<= counter_reg + 1;
end if;
if(counter_reg(0)='1') then
shift_next <= shift_left(shift_reg,1);
end if;
when others => null; -- do nothing, if we are in a different state
end case;
end process NSL;
end Behavioral;

88
spi_driver_tb.vhd
View File

@@ -1,35 +1,13 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:38:41 05/17/2016
-- Design Name:
-- Module Name: /home/timo/vhdl-yasg/spi_driver_tb.vhd
-- Project Name: yasg
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_driver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 15:38:41 05/17/2016
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY spi_driver_tb IS
@@ -56,7 +34,7 @@ ARCHITECTURE behavior OF spi_driver_tb IS
signal rst : std_logic := '0';
signal val : unsigned(11 downto 0) := (others => '0');
--Outputs
--Outputs
signal sck : std_logic;
signal cs : std_logic;
signal mosi : std_logic;
@@ -66,7 +44,7 @@ ARCHITECTURE behavior OF spi_driver_tb IS
BEGIN
-- Instantiate the Unit Under Test (UUT)
-- Instantiate the Unit Under Test (UUT)
uut: spi_driver PORT MAP (
clk => clk,
rst => rst,
@@ -79,36 +57,36 @@ BEGIN
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period*10;
val <= to_unsigned(0,12);
wait for clk_period*64;
val <= to_unsigned(7,12);
wait for clk_period*64;
val <= to_unsigned(31,12);
wait for clk_period*64;
val <= to_unsigned(128,12);
wait for clk_period*64;
val <= to_unsigned(512,12);
wait for clk_period*64;
val <= to_unsigned(0,12);
wait for clk_period*64;
val <= to_unsigned(7,12);
wait for clk_period*64;
val <= to_unsigned(31,12);
wait for clk_period*64;
val <= to_unsigned(128,12);
wait for clk_period*64;
val <= to_unsigned(512,12);
wait for clk_period*64;
-- insert stimulus here