Some experiments with dds. probably useless.
This commit is contained in:
T-moe
26
dds.sym
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26
dds.sym
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@@ -0,0 +1,26 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<symbol version="7" name="dds">
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<symboltype>BLOCK</symboltype>
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<timestamp>2016-5-16T9:25:36</timestamp>
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<pin polarity="Input" x="0" y="-160" name="clk" />
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<pin polarity="Input" x="0" y="-96" name="freq" />
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<pin polarity="Input" x="0" y="-32" name="form(1:0)" />
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<pin polarity="Output" x="384" y="-160" name="update" />
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<pin polarity="Output" x="384" y="-32" name="amp(11:0)" />
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<graph>
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<rect width="256" x="64" y="-192" height="192" />
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<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
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<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
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<line x2="0" y1="-160" y2="-160" x1="64" />
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<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin freq" />
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<line x2="0" y1="-96" y2="-96" x1="64" />
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<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin form(1:0)" />
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<rect width="64" x="0" y="-44" height="24" />
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<line x2="0" y1="-32" y2="-32" x1="64" />
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<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin update" />
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<line x2="384" y1="-160" y2="-160" x1="320" />
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<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin amp(11:0)" />
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<rect width="64" x="320" y="-44" height="24" />
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<line x2="384" y1="-32" y2="-32" x1="320" />
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</graph>
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</symbol>
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66
dds.vhd
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66
dds.vhd
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@@ -0,0 +1,66 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:09:53 05/16/2016
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-- Design Name:
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-- Module Name: dds - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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use work.helpers.all;
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entity dds is
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Generic (clk_freq: natural:= 50000000;
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max_freq: natural := 100000;
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adc_res: natural:=12;
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vector_res: natural :=8 );
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Port ( clk : in STD_LOGIC;
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freq : in unsigned (log2_int(max_freq)-1 downto 0);
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form : in unsigned (1 downto 0);
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amp : out unsigned (adc_res-1 downto 0);
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update : out STD_LOGIC);
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end dds;
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architecture Behavioral of dds is
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constant clk2 : natural := clk_freq/(2**vector_res);
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constant clk2_us :unsigned (log2_int(clk2)-1 downto 0) :=to_unsigned(clk2,log2_int(clk2));
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signal prescale,cnt_prescale :unsigned (log2_int(clk2)-1 downto 0) := (others => '0');
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signal m, idx : unsigned(vector_res -1 downto 0):= (others => '0');
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begin
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prescale <= divide(to_unsigned(clk2,prescale'length),freq);
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m <= resize(divide(freq*prescale,to_unsigned(clk2,prescale'length)),m'length);
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P1: process(clk)
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begin
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if(rising_edge(clk)) then
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if(cnt_prescale >= prescale) then
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cnt_prescale <= to_unsigned(1, prescale'length);
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idx <= (idx+m) mod (2**vector_res);
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else
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cnt_prescale <= cnt_prescale +1;
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end if;
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end if;
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end process P1;
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end Behavioral;
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109
dds_tb.vhd
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109
dds_tb.vhd
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@@ -0,0 +1,109 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:35:57 05/16/2016
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-- Design Name:
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-- Module Name: /home/timo/vhdl-yasg/dds_tb.vhd
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-- Project Name: yasg
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: dds
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY dds_tb IS
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END dds_tb;
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ARCHITECTURE behavior OF dds_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT dds
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PORT(
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clk : IN std_logic;
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freq : IN unsigned(16 downto 0);
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form : IN unsigned(1 downto 0);
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amp : OUT unsigned(11 downto 0);
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update : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal freq : unsigned(16 downto 0) := (others => '0');
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signal form : unsigned(1 downto 0) := (others => '0');
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--Outputs
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signal amp : unsigned(11 downto 0);
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signal update : std_logic;
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: dds PORT MAP (
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clk => clk,
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freq => freq,
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form => form,
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amp => amp,
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update => update
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clk_period*10;
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freq <= to_unsigned(1,17);
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wait for clk_period*10;
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freq <= to_unsigned(10,17);
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wait for clk_period*10;
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freq <= to_unsigned(100,17);
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wait for clk_period*10;
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freq <= to_unsigned(1000,17);
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wait for clk_period*10;
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freq <= to_unsigned(10000,17);
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wait for clk_period*10;
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freq <= to_unsigned(50000,17);
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wait for clk_period*10;
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freq <= to_unsigned(100000,17);
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-- insert stimulus here
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wait;
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end process;
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END;
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46
helpers.vhd
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46
helpers.vhd
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@@ -0,0 +1,46 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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package helpers is
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--helper function to calculate the log2 (truncated) of a integer
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function log2_int(n:natural) return natural;
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function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
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end helpers;
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package body helpers is
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function log2_int(n:natural) return natural is
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begin
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if(n>1) then --we can stil divide n by 2
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return 1+log2_int(n/2); --recursivly call log2_int for the by two divided number.
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end if;
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return 1; --since we can no longer divide n, return 1
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end log2_int;
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--Source: http://vhdlguru.blogspot.ch/2010/03/vhdl-function-for-division-two-signed.html
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function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
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variable a1 : unsigned(a'length-1 downto 0):=a;
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variable b1 : unsigned(b'length-1 downto 0):=b;
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variable p1 : unsigned(b'length downto 0):= (others => '0');
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variable i : integer:=0;
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begin
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for i in 0 to b'length-1 loop
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p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
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p1(0) := a1(a'length-1);
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a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
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p1 := p1-b1;
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if(p1(b'length-1) ='1') then
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a1(0) :='0';
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p1 := p1+b1;
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else
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a1(0) :='1';
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end if;
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end loop;
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return a1;
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end divide;
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end helpers;
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137
yasg.gise
137
yasg.gise
@@ -21,8 +21,141 @@
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="yasg.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name=".lso"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
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<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="dds.cmd_log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="dds.lso"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="dds.ngc"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="dds.ngr"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds.prj"/>
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<file xil_pn:fileType="FILE_SPL" xil_pn:name="dds.spl"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="dds.stx"/>
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<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="dds.sym" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="dds.syr"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="dds.vhi"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="dds.xst"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_envsettings.html"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_summary.html"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="dds_tb_isim_beh.exe"/>
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||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="dds_tb_isim_beh.wdb"/>
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||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_stx_beh.prj"/>
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||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="dds_xst.xrpt"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
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||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
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||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/>
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||||
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/>
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<file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/>
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||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
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||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
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||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
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||||
</files>
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||||
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||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1463390579" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1463390579">
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||||
<status xil_pn:value="SuccessfullyRun"/>
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||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
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||||
<transform xil_pn:end_ts="1463396197" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463396197">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
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||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="dds.vhd"/>
|
||||
<outfile xil_pn:name="dds_tb.vhd"/>
|
||||
<outfile xil_pn:name="helpers.vhd"/>
|
||||
<outfile xil_pn:name="lcd_driver.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463390593" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8944967924106743327" xil_pn:start_ts="1463390593">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463390593" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5140074775533282471" xil_pn:start_ts="1463390593">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463391355" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-5493774896299751744" xil_pn:start_ts="1463391355">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463396205" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463396205">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="dds.vhd"/>
|
||||
<outfile xil_pn:name="dds_tb.vhd"/>
|
||||
<outfile xil_pn:name="helpers.vhd"/>
|
||||
<outfile xil_pn:name="lcd_driver.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463396206" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6917596232395121981" xil_pn:start_ts="1463396205">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="dds_tb_beh.prj"/>
|
||||
<outfile xil_pn:name="dds_tb_isim_beh.exe"/>
|
||||
<outfile xil_pn:name="fuse.log"/>
|
||||
<outfile xil_pn:name="isim"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
<outfile xil_pn:name="xilinxsim.ini"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463405352" xil_pn:in_ck="5986968781955972703" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1463405351">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="dds_tb_isim_beh.wdb"/>
|
||||
<outfile xil_pn:name="isim.cmd"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1463390963">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4734209280692859583" xil_pn:start_ts="1463390963">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5493774896299751744" xil_pn:start_ts="1463390963">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1463390963">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6025362818043660137" xil_pn:start_ts="1463390963">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1463390963">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6649507734898087542" xil_pn:start_ts="1463390963">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1463396180" xil_pn:in_ck="-8475077075915550756" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7698400163542717516" xil_pn:start_ts="1463396172">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name=".lso"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="dds.lso"/>
|
||||
<outfile xil_pn:name="dds.ngc"/>
|
||||
<outfile xil_pn:name="dds.ngr"/>
|
||||
<outfile xil_pn:name="dds.prj"/>
|
||||
<outfile xil_pn:name="dds.stx"/>
|
||||
<outfile xil_pn:name="dds.syr"/>
|
||||
<outfile xil_pn:name="dds.xst"/>
|
||||
<outfile xil_pn:name="dds_tb_beh.prj"/>
|
||||
<outfile xil_pn:name="dds_tb_stx_beh.prj"/>
|
||||
<outfile xil_pn:name="dds_xst.xrpt"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
|
||||
24
yasg.xise
24
yasg.xise
@@ -16,21 +16,38 @@
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3AN Starter Kit" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|lcd_driver|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="lcd_driver.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/lcd_driver" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|dds|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="dds.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/dds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/dds_tb" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.dds_tb" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
@@ -39,6 +56,7 @@
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|dds_tb|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>
|
||||
|
||||
Reference in New Issue
Block a user