67 lines
2.0 KiB
VHDL
67 lines
2.0 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:09:53 05/16/2016
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-- Design Name:
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-- Module Name: dds - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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use work.helpers.all;
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entity dds is
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Generic (clk_freq: natural:= 50000000;
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max_freq: natural := 100000;
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adc_res: natural:=12;
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vector_res: natural :=8 );
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Port ( clk : in STD_LOGIC;
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freq : in unsigned (log2_int(max_freq)-1 downto 0);
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form : in unsigned (1 downto 0);
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amp : out unsigned (adc_res-1 downto 0);
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update : out STD_LOGIC);
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end dds;
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architecture Behavioral of dds is
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constant clk2 : natural := clk_freq/(2**vector_res);
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constant clk2_us :unsigned (log2_int(clk2)-1 downto 0) :=to_unsigned(clk2,log2_int(clk2));
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signal prescale,cnt_prescale :unsigned (log2_int(clk2)-1 downto 0) := (others => '0');
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signal m, idx : unsigned(vector_res -1 downto 0):= (others => '0');
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begin
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prescale <= divide(to_unsigned(clk2,prescale'length),freq);
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m <= resize(divide(freq*prescale,to_unsigned(clk2,prescale'length)),m'length);
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P1: process(clk)
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begin
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if(rising_edge(clk)) then
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if(cnt_prescale >= prescale) then
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cnt_prescale <= to_unsigned(1, prescale'length);
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idx <= (idx+m) mod (2**vector_res);
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else
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cnt_prescale <= cnt_prescale +1;
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end if;
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end if;
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end process P1;
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end Behavioral;
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