From c423df7bf9ecca3677b2795882c71ab3a989552d Mon Sep 17 00:00:00 2001 From: T-moe Date: Mon, 16 May 2016 15:30:18 +0200 Subject: [PATCH] Some experiments with dds. probably useless. --- dds.sym | 26 ++++++++++ dds.vhd | 66 +++++++++++++++++++++++++ dds_tb.vhd | 109 +++++++++++++++++++++++++++++++++++++++++ helpers.vhd | 46 ++++++++++++++++++ yasg.gise | 137 +++++++++++++++++++++++++++++++++++++++++++++++++++- yasg.xise | 24 +++++++-- 6 files changed, 403 insertions(+), 5 deletions(-) create mode 100644 dds.sym create mode 100644 dds.vhd create mode 100644 dds_tb.vhd create mode 100644 helpers.vhd diff --git a/dds.sym b/dds.sym new file mode 100644 index 0000000..09f9a87 --- /dev/null +++ b/dds.sym @@ -0,0 +1,26 @@ + + + BLOCK + 2016-5-16T9:25:36 + + + + + + + + + + + + + + + + + + + + + + diff --git a/dds.vhd b/dds.vhd new file mode 100644 index 0000000..77f1645 --- /dev/null +++ b/dds.vhd @@ -0,0 +1,66 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:09:53 05/16/2016 +-- Design Name: +-- Module Name: dds - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +use work.helpers.all; + +entity dds is + Generic (clk_freq: natural:= 50000000; + max_freq: natural := 100000; + adc_res: natural:=12; + vector_res: natural :=8 ); + Port ( clk : in STD_LOGIC; + freq : in unsigned (log2_int(max_freq)-1 downto 0); + form : in unsigned (1 downto 0); + amp : out unsigned (adc_res-1 downto 0); + update : out STD_LOGIC); +end dds; + +architecture Behavioral of dds is + constant clk2 : natural := clk_freq/(2**vector_res); + constant clk2_us :unsigned (log2_int(clk2)-1 downto 0) :=to_unsigned(clk2,log2_int(clk2)); + signal prescale,cnt_prescale :unsigned (log2_int(clk2)-1 downto 0) := (others => '0'); + signal m, idx : unsigned(vector_res -1 downto 0):= (others => '0'); + +begin + prescale <= divide(to_unsigned(clk2,prescale'length),freq); + m <= resize(divide(freq*prescale,to_unsigned(clk2,prescale'length)),m'length); + + P1: process(clk) + begin + if(rising_edge(clk)) then + if(cnt_prescale >= prescale) then + cnt_prescale <= to_unsigned(1, prescale'length); + idx <= (idx+m) mod (2**vector_res); + else + cnt_prescale <= cnt_prescale +1; + end if; + end if; + end process P1; + + +end Behavioral; + diff --git a/dds_tb.vhd b/dds_tb.vhd new file mode 100644 index 0000000..c954bbf --- /dev/null +++ b/dds_tb.vhd @@ -0,0 +1,109 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:35:57 05/16/2016 +-- Design Name: +-- Module Name: /home/timo/vhdl-yasg/dds_tb.vhd +-- Project Name: yasg +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: dds +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY dds_tb IS +END dds_tb; + +ARCHITECTURE behavior OF dds_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT dds + PORT( + clk : IN std_logic; + freq : IN unsigned(16 downto 0); + form : IN unsigned(1 downto 0); + amp : OUT unsigned(11 downto 0); + update : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal freq : unsigned(16 downto 0) := (others => '0'); + signal form : unsigned(1 downto 0) := (others => '0'); + + --Outputs + signal amp : unsigned(11 downto 0); + signal update : std_logic; + + -- Clock period definitions + constant clk_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: dds PORT MAP ( + clk => clk, + freq => freq, + form => form, + amp => amp, + update => update + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 100 ns; + + wait for clk_period*10; + freq <= to_unsigned(1,17); + wait for clk_period*10; + freq <= to_unsigned(10,17); + wait for clk_period*10; + freq <= to_unsigned(100,17); + wait for clk_period*10; + freq <= to_unsigned(1000,17); + wait for clk_period*10; + freq <= to_unsigned(10000,17); + wait for clk_period*10; + freq <= to_unsigned(50000,17); + wait for clk_period*10; + freq <= to_unsigned(100000,17); + + -- insert stimulus here + + wait; + end process; + +END; diff --git a/helpers.vhd b/helpers.vhd new file mode 100644 index 0000000..b0e3105 --- /dev/null +++ b/helpers.vhd @@ -0,0 +1,46 @@ + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +package helpers is + --helper function to calculate the log2 (truncated) of a integer + function log2_int(n:natural) return natural; + function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED; +end helpers; + + + +package body helpers is + function log2_int(n:natural) return natural is + begin + if(n>1) then --we can stil divide n by 2 + return 1+log2_int(n/2); --recursivly call log2_int for the by two divided number. + end if; + return 1; --since we can no longer divide n, return 1 + end log2_int; + + --Source: http://vhdlguru.blogspot.ch/2010/03/vhdl-function-for-division-two-signed.html + function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is + variable a1 : unsigned(a'length-1 downto 0):=a; + variable b1 : unsigned(b'length-1 downto 0):=b; + variable p1 : unsigned(b'length downto 0):= (others => '0'); + variable i : integer:=0; + + begin + for i in 0 to b'length-1 loop + p1(b'length-1 downto 1) := p1(b'length-2 downto 0); + p1(0) := a1(a'length-1); + a1(a'length-1 downto 1) := a1(a'length-2 downto 0); + p1 := p1-b1; + if(p1(b'length-1) ='1') then + a1(0) :='0'; + p1 := p1+b1; + else + a1(0) :='1'; + end if; + end loop; + return a1; + end divide; +end helpers; + diff --git a/yasg.gise b/yasg.gise index cfaaefd..9b04e0d 100644 --- a/yasg.gise +++ b/yasg.gise @@ -21,8 +21,141 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/yasg.xise b/yasg.xise index 514e35c..87f2d52 100644 --- a/yasg.xise +++ b/yasg.xise @@ -16,21 +16,38 @@ + + + + + + + + + + + + + + + - - - + + + + + @@ -39,6 +56,7 @@ +