Some experiments with dds. probably useless.

dds.sym

@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="dds">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2016-5-16T9:25:36</timestamp>
+    <pin polarity="Input" x="0" y="-160" name="clk" />
+    <pin polarity="Input" x="0" y="-96" name="freq" />
+    <pin polarity="Input" x="0" y="-32" name="form(1:0)" />
+    <pin polarity="Output" x="384" y="-160" name="update" />
+    <pin polarity="Output" x="384" y="-32" name="amp(11:0)" />
+    <graph>
+        <rect width="256" x="64" y="-192" height="192" />
+        <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
+        <line x2="0" y1="-160" y2="-160" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin freq" />
+        <line x2="0" y1="-96" y2="-96" x1="64" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin form(1:0)" />
+        <rect width="64" x="0" y="-44" height="24" />
+        <line x2="0" y1="-32" y2="-32" x1="64" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin update" />
+        <line x2="384" y1="-160" y2="-160" x1="320" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin amp(11:0)" />
+        <rect width="64" x="320" y="-44" height="24" />
+        <line x2="384" y1="-32" y2="-32" x1="320" />
+    </graph>
+</symbol>

dds.vhd

@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    11:09:53 05/16/2016 
+-- Design Name: 
+-- Module Name:    dds - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+use work.helpers.all;
+
+entity dds is
+    Generic (clk_freq: natural:= 50000000;
+             max_freq: natural := 100000;
+             adc_res: natural:=12;
+             vector_res: natural :=8 );
+    Port ( clk : in  STD_LOGIC;
+           freq : in  unsigned (log2_int(max_freq)-1 downto 0);
+           form : in  unsigned (1 downto 0);
+           amp : out  unsigned (adc_res-1 downto 0);
+           update : out  STD_LOGIC);
+end dds;
+
+architecture Behavioral of dds is
+    constant clk2 : natural := clk_freq/(2**vector_res);
+    constant clk2_us :unsigned (log2_int(clk2)-1 downto 0) :=to_unsigned(clk2,log2_int(clk2));
+    signal prescale,cnt_prescale :unsigned (log2_int(clk2)-1 downto 0) := (others => '0');   
+    signal m, idx : unsigned(vector_res -1  downto 0):= (others => '0');   
+    
+begin
+    prescale <= divide(to_unsigned(clk2,prescale'length),freq);
+    m <= resize(divide(freq*prescale,to_unsigned(clk2,prescale'length)),m'length);
+    
+    P1: process(clk) 
+    begin
+        if(rising_edge(clk)) then
+            if(cnt_prescale >= prescale) then
+                cnt_prescale <= to_unsigned(1, prescale'length);
+                idx <= (idx+m) mod (2**vector_res);
+            else
+                cnt_prescale <= cnt_prescale +1;
+            end if;
+        end if;
+    end process P1;
+
+
+end Behavioral;
+

dds_tb.vhd

@@ -0,0 +1,109 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   11:35:57 05/16/2016
+-- Design Name:   
+-- Module Name:   /home/timo/vhdl-yasg/dds_tb.vhd
+-- Project Name:  yasg
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: dds
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+ 
+ENTITY dds_tb IS
+END dds_tb;
+ 
+ARCHITECTURE behavior OF dds_tb IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT dds
+    PORT(
+         clk : IN  std_logic;
+         freq : IN  unsigned(16 downto 0);
+         form : IN  unsigned(1 downto 0);
+         amp : OUT  unsigned(11 downto 0);
+         update : OUT  std_logic
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk : std_logic := '0';
+   signal freq : unsigned(16 downto 0) := (others => '0');
+   signal form : unsigned(1 downto 0) := (others => '0');
+
+ 	--Outputs
+   signal amp : unsigned(11 downto 0);
+   signal update : std_logic;
+
+   -- Clock period definitions
+   constant clk_period : time := 10 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: dds PORT MAP (
+          clk => clk,
+          freq => freq,
+          form => form,
+          amp => amp,
+          update => update
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+		clk <= '0';
+		wait for clk_period/2;
+		clk <= '1';
+		wait for clk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state for 100 ns.
+      wait for 100 ns;	
+
+      wait for clk_period*10;
+      freq <= to_unsigned(1,17);
+        wait for clk_period*10;
+      freq <= to_unsigned(10,17);
+        wait for clk_period*10;
+      freq <= to_unsigned(100,17);
+        wait for clk_period*10;
+      freq <= to_unsigned(1000,17);
+      wait for clk_period*10;
+      freq <= to_unsigned(10000,17);
+      wait for clk_period*10;
+      freq <= to_unsigned(50000,17);
+      wait for clk_period*10;
+      freq <= to_unsigned(100000,17);
+
+      -- insert stimulus here 
+
+      wait;
+   end process;
+
+END;

helpers.vhd

@@ -0,0 +1,46 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+package helpers is
+    --helper function to calculate the log2 (truncated) of a integer
+    function log2_int(n:natural) return natural; 
+    function divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
+end helpers;
+
+
+
+package body helpers is
+    function log2_int(n:natural) return natural is
+        begin
+          if(n>1) then --we can stil divide n by 2
+                return 1+log2_int(n/2); --recursivly call log2_int for the by two divided number.
+          end if;
+          return 1; --since we can no longer divide n, return 1
+    end log2_int;
+    
+    --Source: http://vhdlguru.blogspot.ch/2010/03/vhdl-function-for-division-two-signed.html
+    function  divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
+    variable a1 : unsigned(a'length-1 downto 0):=a;
+    variable b1 : unsigned(b'length-1 downto 0):=b;
+    variable p1 : unsigned(b'length downto 0):= (others => '0');
+    variable i : integer:=0;
+
+    begin
+        for i in 0 to b'length-1 loop
+            p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
+            p1(0) := a1(a'length-1);
+            a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
+            p1 := p1-b1;
+            if(p1(b'length-1) ='1') then
+                a1(0) :='0';
+                p1 := p1+b1;
+            else
+                a1(0) :='1';
+            end if;
+        end loop;
+        return a1;
+    end divide;
+end helpers;
+

yasg.gise

@@ -21,8 +21,141 @@
 
   <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="yasg.xise"/>
 
-  <files xmlns="http://www.xilinx.com/XMLSchema"/>
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name=".lso"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="dds.cmd_log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="dds.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="dds.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="dds.ngr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds.prj"/>
+    <file xil_pn:fileType="FILE_SPL" xil_pn:name="dds.spl"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="dds.stx"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="dds.sym" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="dds.syr"/>
+    <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="dds.vhi"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="dds.xst"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_envsettings.html"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_summary.html"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_beh.prj"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="dds_tb_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="dds_tb_isim_beh.wdb"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_stx_beh.prj"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="dds_xst.xrpt"/>
+    <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/>
+    <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/>
+    <file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
+  </files>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1463390579" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1463390579">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463396197" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463396197">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="dds.vhd"/>
+      <outfile xil_pn:name="dds_tb.vhd"/>
+      <outfile xil_pn:name="helpers.vhd"/>
+      <outfile xil_pn:name="lcd_driver.vhd"/>
+    </transform>
+    <transform xil_pn:end_ts="1463390593" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8944967924106743327" xil_pn:start_ts="1463390593">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463390593" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5140074775533282471" xil_pn:start_ts="1463390593">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463391355" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-5493774896299751744" xil_pn:start_ts="1463391355">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463396205" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463396205">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="dds.vhd"/>
+      <outfile xil_pn:name="dds_tb.vhd"/>
+      <outfile xil_pn:name="helpers.vhd"/>
+      <outfile xil_pn:name="lcd_driver.vhd"/>
+    </transform>
+    <transform xil_pn:end_ts="1463396206" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6917596232395121981" xil_pn:start_ts="1463396205">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="dds_tb_beh.prj"/>
+      <outfile xil_pn:name="dds_tb_isim_beh.exe"/>
+      <outfile xil_pn:name="fuse.log"/>
+      <outfile xil_pn:name="isim"/>
+      <outfile xil_pn:name="isim.log"/>
+      <outfile xil_pn:name="xilinxsim.ini"/>
+    </transform>
+    <transform xil_pn:end_ts="1463405352" xil_pn:in_ck="5986968781955972703" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1463405351">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="dds_tb_isim_beh.wdb"/>
+      <outfile xil_pn:name="isim.cmd"/>
+      <outfile xil_pn:name="isim.log"/>
+    </transform>
+    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1463390963">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4734209280692859583" xil_pn:start_ts="1463390963">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5493774896299751744" xil_pn:start_ts="1463390963">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1463390963">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6025362818043660137" xil_pn:start_ts="1463390963">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1463390963">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6649507734898087542" xil_pn:start_ts="1463390963">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1463396180" xil_pn:in_ck="-8475077075915550756" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7698400163542717516" xil_pn:start_ts="1463396172">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name=".lso"/>
+      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
+      <outfile xil_pn:name="dds.lso"/>
+      <outfile xil_pn:name="dds.ngc"/>
+      <outfile xil_pn:name="dds.ngr"/>
+      <outfile xil_pn:name="dds.prj"/>
+      <outfile xil_pn:name="dds.stx"/>
+      <outfile xil_pn:name="dds.syr"/>
+      <outfile xil_pn:name="dds.xst"/>
+      <outfile xil_pn:name="dds_tb_beh.prj"/>
+      <outfile xil_pn:name="dds_tb_stx_beh.prj"/>
+      <outfile xil_pn:name="dds_xst.xrpt"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+      <outfile xil_pn:name="xst"/>
+    </transform>
+  </transforms>
 
 </generated_project>

yasg.xise

@@ -16,21 +16,38 @@
 
   <files>
     <file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
+    <file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
+    </file>
   </files>
 
   <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3AN Starter Kit" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|lcd_driver|Behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|dds|Behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="lcd_driver.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="dds.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/lcd_driver" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/dds" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/dds_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.dds_tb" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -39,6 +56,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|dds_tb|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>