Added file headers. Added New Toplevel Screenshot

controller.vhd

@@ -1,34 +1,15 @@
 ----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer: 
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
--- 
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:		    GPL v3
 -- Create Date:    18:47:36 05/23/2016 
--- Design Name: 
--- Module Name:    controller - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 use IEEE.NUMERIC_STD.ALL;
 
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity controller is
     Port ( clk : in  STD_LOGIC;
 			  rst: in STD_LOGIC;

controller_tb.vhd

@@ -1,35 +1,13 @@
---------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer:
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
---
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:		    GPL v3
 -- Create Date:    20:08:51 06/06/2016
--- Design Name:   
--- Module Name:   /home/timo/workspace/vhdl-yasg/controller_tb.vhd
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: controller
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
 --------------------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
  
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 USE ieee.numeric_std.ALL;
  
 ENTITY controller_tb IS

dds.vhd

@@ -1,22 +1,11 @@
 ----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer: 
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
--- 
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:		    GPL v3
 -- Create Date:    11:09:53 05/16/2016 
--- Design Name: 
--- Module Name:    dds - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;

dds_tb.vhd

@@ -1,30 +1,11 @@
---------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer:
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
---
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:		    GPL v3
 -- Create Date:    11:35:57 05/16/2016
--- Design Name:   
--- Module Name:   /home/timo/vhdl-yasg/dds_tb.vhd
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: dds
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
 --------------------------------------------------------------------------------
+
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.numeric_std.ALL;

io.ucf

@@ -1,3 +1,11 @@
+#---------------------------------------------------------------------------------
+#- Project:        YASG (Yet another signal generator)
+#- Project Page:   https://github.com/id101010/vhdl-yasg/
+#- Authors:        Aaron Schmocker & Timo Lang
+#- License:		    GPL v3
+#- Create Date:    16:23:12 05/20/2016 
+#---------------------------------------------------------------------------------
+
 NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
 NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
 

iseconfig/filter.filter

@@ -6,8 +6,8 @@
 <filters xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation='filter.xsd'>
 <filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_8</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
 <filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_6</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
-<filter task="xst" file="Xst" num="643" type="warning"><arg index="1" match_type="wildcard">/home/timo/workspace/vhdl-yasg/controller.vhd</arg><arg index="2" match_type="wildcard">169</arg><arg index="3" match_type="wildcard">*</arg><arg index="4" match_type="wildcard">*</arg><arg index="5" match_type="wildcard">17</arg></filter>
+<filter task="xst" file="Xst" num="643" type="warning"><arg index="1">/home/timo/workspace/vhdl-yasg/controller.vhd</arg><arg index="2" match_type="wildcard">*</arg><arg index="3" match_type="wildcard">*</arg><arg index="4" match_type="wildcard">*</arg><arg index="5">17</arg></filter>
 <filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_7</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
-<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_reg_0</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
+<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_reg_0</arg><arg index="2" match_type="wildcard">*</arg><arg index="3">controller</arg></filter>
 <filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">lcd_data_reg_7</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
 </filters>

lcd_driver.vhd

@@ -1,45 +1,15 @@
 ----------------------------------------------------------------------------------
--- This program is free software: you can redistribute it and/or modify
+-- Project:        YASG (Yet another signal generator)
--- it under the terms of the GNU General Public License as published by
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
--- the Free Software Foundation, either version 3 of the License, or
+-- Authors:        Aaron Schmocker & Timo Lang
--- (at your option) any later version.
+-- License:		    GPL v3
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------------
--- Company:         Berner Fachhochschule
--- Engineer:        Aaron Schmocker
--- 
 -- Create Date:    19:29:54 05/09/2016 
--- Design Name: 
--- Module Name:     lcddriver - Behavioral 
--- Project Name:    yasg
--- Target Devices:  Spartan-3am Board
--- Tool versions: 
--- Description:     This file is part of the yasg project
---
--- Dependencies: 
---
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity lcd_driver is
     generic (   NBITS           : natural := 21;        -- counter bit size

lcd_driver_tb.vhd

@@ -1,37 +1,14 @@
---------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer:
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
---
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:		    GPL v3
 -- Create Date:    21:11:41 05/16/2016
--- Design Name:   
+----------------------------------------------------------------------------------
--- Module Name:   /home/aaron/Dokumente/STUDIUM/SEM6/EloSys/EloSysDigital/Projekt/vhdl-yasg/lcd_driver_tb.vhd
+
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: lcd_driver
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
  
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
 ENTITY lcd_driver_tb IS
 END lcd_driver_tb;
  

rotary.vhd

@@ -1,8 +1,10 @@
------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
---
+-- Project:        YASG (Yet another signal generator)
--- Decoder für Drehgeber
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
---
+-- Authors:        Aaron Schmocker & Timo Lang
------------------------------------------------------------------------------
+-- License:		    GPL v3
+-- Create Date:    19:07:22 05/23/2016 
+----------------------------------------------------------------------------------
  
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

spi_driver.vhd

@@ -1,31 +1,15 @@
 ----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer: 
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
--- 
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:		    GPL v3
 -- Create Date:    12:51:31 05/17/2016 
--- Design Name: 
--- Module Name:    spi_driver - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity spi_driver is
 	Generic (clk_freq: natural:= 50000000;
              adc_res: natural:=12);

spi_driver_tb.vhd

@@ -1,35 +1,13 @@
---------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
--- Company: 
+-- Project:        YASG (Yet another signal generator)
--- Engineer:
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
---
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:		    GPL v3
 -- Create Date:    15:38:41 05/17/2016
--- Design Name:   
+----------------------------------------------------------------------------------
--- Module Name:   /home/timo/vhdl-yasg/spi_driver_tb.vhd
+
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: spi_driver
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 USE ieee.numeric_std.ALL;
  
 ENTITY spi_driver_tb IS