diff --git a/controller.vhd b/controller.vhd index 4967cfb..a191329 100644 --- a/controller.vhd +++ b/controller.vhd @@ -1,34 +1,15 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: --- +-- Project: YASG (Yet another signal generator) +-- Project Page: https://github.com/id101010/vhdl-yasg/ +-- Authors: Aaron Schmocker & Timo Lang +-- License: GPL v3 -- Create Date: 18:47:36 05/23/2016 --- Design Name: --- Module Name: controller - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ---------------------------------------------------------------------------------- + library IEEE; use IEEE.STD_LOGIC_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity controller is Port ( clk : in STD_LOGIC; rst: in STD_LOGIC; diff --git a/controller_tb.vhd b/controller_tb.vhd index 196c2e0..9809fe8 100644 --- a/controller_tb.vhd +++ b/controller_tb.vhd @@ -1,35 +1,13 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 20:08:51 06/06/2016 --- Design Name: --- Module Name: /home/timo/workspace/vhdl-yasg/controller_tb.vhd --- Project Name: yasg --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: controller --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. +---------------------------------------------------------------------------------- +-- Project: YASG (Yet another signal generator) +-- Project Page: https://github.com/id101010/vhdl-yasg/ +-- Authors: Aaron Schmocker & Timo Lang +-- License: GPL v3 +-- Create Date: 20:08:51 06/06/2016 -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY controller_tb IS diff --git a/dds.vhd b/dds.vhd index 4d11b02..906c01f 100644 --- a/dds.vhd +++ b/dds.vhd @@ -1,22 +1,11 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: --- +-- Project: YASG (Yet another signal generator) +-- Project Page: https://github.com/id101010/vhdl-yasg/ +-- Authors: Aaron Schmocker & Timo Lang +-- License: GPL v3 -- Create Date: 11:09:53 05/16/2016 --- Design Name: --- Module Name: dds - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ---------------------------------------------------------------------------------- + library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; diff --git a/dds_tb.vhd b/dds_tb.vhd index 73b1259..389b7c8 100644 --- a/dds_tb.vhd +++ b/dds_tb.vhd @@ -1,30 +1,11 @@ +---------------------------------------------------------------------------------- +-- Project: YASG (Yet another signal generator) +-- Project Page: https://github.com/id101010/vhdl-yasg/ +-- Authors: Aaron Schmocker & Timo Lang +-- License: GPL v3 +-- Create Date: 11:35:57 05/16/2016 -------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:35:57 05/16/2016 --- Design Name: --- Module Name: /home/timo/vhdl-yasg/dds_tb.vhd --- Project Name: yasg --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: dds --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- + LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; diff --git a/io.ucf b/io.ucf index 97ccd4b..33b508d 100644 --- a/io.ucf +++ b/io.ucf @@ -1,3 +1,11 @@ +#--------------------------------------------------------------------------------- +#- Project: YASG (Yet another signal generator) +#- Project Page: https://github.com/id101010/vhdl-yasg/ +#- Authors: Aaron Schmocker & Timo Lang +#- License: GPL v3 +#- Create Date: 16:23:12 05/20/2016 +#--------------------------------------------------------------------------------- + NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ; NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%; diff --git a/iseconfig/filter.filter b/iseconfig/filter.filter index 94081c7..9fc90c1 100644 --- a/iseconfig/filter.filter +++ b/iseconfig/filter.filter @@ -6,8 +6,8 @@ ret_state_80lcd_driver ret_state_60lcd_driver -/home/timo/workspace/vhdl-yasg/controller.vhd169**17 +/home/timo/workspace/vhdl-yasg/controller.vhd***17 ret_state_70lcd_driver -ret_state_reg_00controller +ret_state_reg_0*controller lcd_data_reg_70controller diff --git a/lcd_driver.vhd b/lcd_driver.vhd index 77250b8..c83d45d 100644 --- a/lcd_driver.vhd +++ b/lcd_driver.vhd @@ -1,45 +1,15 @@ ---------------------------------------------------------------------------------- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . ----------------------------------------------------------------------------------- --- Company: Berner Fachhochschule --- Engineer: Aaron Schmocker --- --- Create Date: 19:29:54 05/09/2016 --- Design Name: --- Module Name: lcddriver - Behavioral --- Project Name: yasg --- Target Devices: Spartan-3am Board --- Tool versions: --- Description: This file is part of the yasg project --- --- Dependencies: --- --- Additional Comments: --- +-- Project: YASG (Yet another signal generator) +-- Project Page: https://github.com/id101010/vhdl-yasg/ +-- Authors: Aaron Schmocker & Timo Lang +-- License: GPL v3 +-- Create Date: 19:29:54 05/09/2016 ---------------------------------------------------------------------------------- + library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; entity lcd_driver is generic ( NBITS : natural := 21; -- counter bit size diff --git a/lcd_driver_tb.vhd b/lcd_driver_tb.vhd index ef750fb..8f382f9 100644 --- a/lcd_driver_tb.vhd +++ b/lcd_driver_tb.vhd @@ -1,37 +1,14 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:11:41 05/16/2016 --- Design Name: --- Module Name: /home/aaron/Dokumente/STUDIUM/SEM6/EloSys/EloSysDigital/Projekt/vhdl-yasg/lcd_driver_tb.vhd --- Project Name: yasg --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: lcd_driver --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- +---------------------------------------------------------------------------------- +-- Project: YASG (Yet another signal generator) +-- Project Page: https://github.com/id101010/vhdl-yasg/ +-- Authors: Aaron Schmocker & Timo Lang +-- License: GPL v3 +-- Create Date: 21:11:41 05/16/2016 +---------------------------------------------------------------------------------- + LIBRARY ieee; USE ieee.std_logic_1164.ALL; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - ENTITY lcd_driver_tb IS END lcd_driver_tb; diff --git a/rotary.vhd b/rotary.vhd index 8c39568..38e0b2c 100644 --- a/rotary.vhd +++ b/rotary.vhd @@ -1,8 +1,10 @@ ------------------------------------------------------------------------------ --- --- Decoder für Drehgeber --- ------------------------------------------------------------------------------ +---------------------------------------------------------------------------------- +-- Project: YASG (Yet another signal generator) +-- Project Page: https://github.com/id101010/vhdl-yasg/ +-- Authors: Aaron Schmocker & Timo Lang +-- License: GPL v3 +-- Create Date: 19:07:22 05/23/2016 +---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; diff --git a/screenshots/Toplevel.png b/screenshots/Toplevel.png deleted file mode 100644 index 5d3cc96..0000000 Binary files a/screenshots/Toplevel.png and /dev/null differ diff --git a/screenshots/topschema.png b/screenshots/topschema.png new file mode 100644 index 0000000..1f08ac8 Binary files /dev/null and b/screenshots/topschema.png differ diff --git a/spi_driver.vhd b/spi_driver.vhd index 582de95..227c605 100644 --- a/spi_driver.vhd +++ b/spi_driver.vhd @@ -1,31 +1,15 @@ ---------------------------------------------------------------------------------- --- Company: --- Engineer: --- +-- Project: YASG (Yet another signal generator) +-- Project Page: https://github.com/id101010/vhdl-yasg/ +-- Authors: Aaron Schmocker & Timo Lang +-- License: GPL v3 -- Create Date: 12:51:31 05/17/2016 --- Design Name: --- Module Name: spi_driver - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ---------------------------------------------------------------------------------- + library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - entity spi_driver is Generic (clk_freq: natural:= 50000000; adc_res: natural:=12); diff --git a/spi_driver_tb.vhd b/spi_driver_tb.vhd index a8c72b3..69306c9 100644 --- a/spi_driver_tb.vhd +++ b/spi_driver_tb.vhd @@ -1,35 +1,13 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15:38:41 05/17/2016 --- Design Name: --- Module Name: /home/timo/vhdl-yasg/spi_driver_tb.vhd --- Project Name: yasg --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: spi_driver --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- +---------------------------------------------------------------------------------- +-- Project: YASG (Yet another signal generator) +-- Project Page: https://github.com/id101010/vhdl-yasg/ +-- Authors: Aaron Schmocker & Timo Lang +-- License: GPL v3 +-- Create Date: 15:38:41 05/17/2016 +---------------------------------------------------------------------------------- + LIBRARY ieee; USE ieee.std_logic_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY spi_driver_tb IS