Added file headers. Added New Toplevel Screenshot

controller_tb.vhd

@@ -1,35 +1,13 @@
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--- Company: 
--- Engineer:
---
--- Create Date:   20:08:51 06/06/2016
--- Design Name:   
--- Module Name:   /home/timo/workspace/vhdl-yasg/controller_tb.vhd
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: controller
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:		    GPL v3
+-- Create Date:    20:08:51 06/06/2016
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 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
  
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 USE ieee.numeric_std.ALL;
  
 ENTITY controller_tb IS