Added file headers. Added New Toplevel Screenshot

controller.vhd

@@ -1,34 +1,15 @@
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--- Company: 
--- Engineer: 
--- 
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:		    GPL v3
 -- Create Date:    18:47:36 05/23/2016 
--- Design Name: 
--- Module Name:    controller - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
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+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 use IEEE.NUMERIC_STD.ALL;
 
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity controller is
     Port ( clk : in  STD_LOGIC;
 			  rst: in STD_LOGIC;