aaron/vhdl-yasg
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Debounced rotary button

Browse Source
This commit is contained in:
T-moe
2016-06-13 13:28:09 +02:00
parent f0960edf3c
commit 0d566ce4de
4 changed files with 93 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
rotary.vhd
View File

@@ -12,8 +12,10 @@ entity rotary_dec is
Port ( clk : in std_logic; -- Systemtakt
A : in std_logic; -- Spur A
B : in std_logic; -- Spur B
right : out std_logic; -- Zaehlrichtung
ce : out std_logic); -- Clock Enable
btn : in std_logic; -- Button Input
btn_deb : out std_logic; -- Button entprellt
enc_right: out std_logic; -- Zaehlrichtung
enc_ce : out std_logic); -- Clock Enable
end rotary_dec;
@@ -21,7 +23,10 @@ architecture Behavioral of rotary_dec is
signal a_old, b_old: std_logic := '0';
signal a_debounced_reg, a_debounced_next, b_debounced_reg, b_debounced_next : std_logic := '0';
signal counter_a_reg, counter_a_next, counter_b_reg, counter_b_next: unsigned(23 downto 0) := (others => '0');
signal btn_reg, btn_next: std_logic :='0';
signal counter_a_reg, counter_a_next,
counter_b_reg, counter_b_next,
counter_btn_reg, counter_btn_next: unsigned(23 downto 0) := (others => '0');
constant count_max: unsigned(23 downto 0) := to_unsigned(500000,24); --10ms
begin
@@ -31,15 +36,19 @@ begin
if rising_edge(clk) then
counter_a_reg <= counter_a_next;
counter_b_reg <= counter_b_next;
counter_btn_reg <= counter_btn_next;
a_debounced_reg <= a_debounced_next;
b_debounced_reg <= b_debounced_next;
a_old <= a_debounced_reg;
b_old <= b_debounced_reg;
btn_reg <= btn_next;
end if;
end process;
process(A,B, a_debounced_reg, b_debounced_reg, counter_a_reg, counter_b_reg)
btn_deb <= btn_reg;
process(A,B, a_debounced_reg, b_debounced_reg, counter_a_reg, counter_b_reg, btn_reg, btn, counter_btn_reg)
begin
if(A /= a_debounced_reg and counter_a_reg > count_max) then
@@ -57,6 +66,14 @@ begin
b_debounced_next <= b_debounced_reg;
counter_b_next <= counter_b_reg + 1;
end if;
if(btn /= btn_reg and counter_btn_reg > count_max) then
btn_next <= btn;
counter_btn_next <= (others => '0');
else
btn_next <= btn_reg;
counter_btn_next <= counter_btn_reg + 1;
end if;
end process;
@@ -68,9 +85,9 @@ variable state: std_logic_vector(3 downto 0);
begin
state := a_debounced_reg & b_debounced_reg & a_old & b_old;
case state is
when "0001" => right <= '0'; ce <= '1';
when "0010" => right <= '1'; ce <= '1';
when others => right <= '0'; ce <= '0';
when "0001" => enc_right <= '0'; enc_ce <= '1';
when "0010" => enc_right <= '1'; enc_ce <= '1';
when others => enc_right <= '0'; enc_ce <= '0';
end case;
end process;