71 lines
1.6 KiB
VHDL
71 lines
1.6 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 18:47:36 05/23/2016
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-- Design Name:
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-- Module Name: controller - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity controller is
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Port ( clk : in STD_LOGIC;
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rst: in STD_LOGIC;
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enc_updown : in STD_LOGIC;
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enc_ce : in STD_LOGIC;
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enc_err : in STD_LOGIC;
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freq_out : out unsigned (16 downto 0));
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end controller;
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architecture Behavioral of controller is
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signal freq_reg, freq_next : unsigned(16 downto 0) := to_unsigned(1000,17);
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begin
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proc1: process(clk,rst)
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begin
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if(rst='1') then
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freq_reg <= to_unsigned(1000,17);
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elsif(rising_edge(clk)) then
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freq_reg <= freq_next;
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end if;
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end process proc1;
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freq_out <= freq_reg;
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proc2: process(freq_reg,enc_updown,enc_ce,enc_err)
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begin
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freq_next <= freq_reg;
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if(enc_ce='1' and enc_err='0') then
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if(enc_updown='1') then
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freq_next <= freq_reg + 1;
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else
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freq_next <= freq_reg - 1;
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end if;
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end if;
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end process proc2;
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end Behavioral;
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