aaron/vhdl-yasg

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T-moe b0f5d5fbca Added SPI driver.

2016-05-17 15:57:43 +02:00

.gitignore

Initial commit

2016-05-09 19:17:21 +02:00

dds_tb.vhd

Finalized first version of dds.

2016-05-17 12:25:10 +02:00

dds.sym

Some experiments with dds. probably useless.

2016-05-16 15:30:18 +02:00

dds.vhd

Finalized first version of dds.

2016-05-17 12:25:10 +02:00

helpers.vhd

Some experiments with dds. probably useless.

2016-05-16 15:30:18 +02:00

lcd_driver.vhd

Added lcd_driver template.

2016-05-09 19:48:12 +02:00

LICENSE

Initial commit

2016-05-09 19:17:21 +02:00

README.md

Initial commit

2016-05-09 19:17:21 +02:00

spi_driver_tb.vhd

Added SPI driver.

2016-05-17 15:57:43 +02:00

spi_driver.vhd

Added SPI driver.

2016-05-17 15:57:43 +02:00

yasg.gise

Added SPI driver.

2016-05-17 15:57:43 +02:00

yasg.xise

Added SPI driver.

2016-05-17 15:57:43 +02:00

README.md

vhdl-yasg

YASG is yet another signal generator, written in vhdl. It uses Direct Digital Synthesis (DDS) for signal generation. The hardware used will be a Xilinx Spartan-3AN eval board which brings a 12bit analog to digital converter. The boards rotary encoder is used as primary input (choosing signal form and frequency) and the 16x2 LC-Display as optical output.

Used hardware

Xilinx Spartan-3AN Eval Board

Used software

Xilinx
Git
LibreOffice
VIM