265 lines
10 KiB
VHDL
265 lines
10 KiB
VHDL
----------------------------------------------------------------------------------
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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----------------------------------------------------------------------------------
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-- Company: Berner Fachhochschule
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-- Engineer: Aaron Schmocker
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--
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-- Create Date: 19:29:54 05/09/2016
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-- Design Name:
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-- Module Name: lcddriver - Behavioral
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-- Project Name: yasg
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-- Target Devices: Spartan-3am Board
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-- Tool versions:
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-- Description: This file is part of the yasg project
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity lcd_driver is
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generic ( NBITS : natural := 21; -- counter bit size
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clk_freq : natural := 50000000; -- frequency of clk (50MHz) in hz
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wait_40000us : natural := 40000; -- wait 40ms
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wait_37us : natural := 37; -- wait 37us
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wait_1520us : natural := 1520); -- wait 1.52ms
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Port ( clk : in STD_LOGIC; -- Systemclock (50MHz)
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reset : in STD_LOGIC; -- Initialize display controller
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data : in STD_LOGIC_VECTOR (7 downto 0); -- either one ascii char (8bit) or new cursor position (0-31)
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new_character : in STD_LOGIC; -- a new character is available on the data bus
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new_pos : in STD_LOGIC; -- a new cursor position is available on the data bus
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auto_incr_cursor : in STD_LOGIC; -- the cursor should automatically be incremented after writing a new character
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lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd databus
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lcd_en : out STD_LOGIC; -- lcd enable
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lcd_rw : out STD_LOGIC; -- lcd read/write
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lcd_rs : out STD_LOGIC); -- lcd register select
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end lcd_driver;
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architecture Behavioral of lcd_driver is
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-- type definitions
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type display_state is (
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INIT, -- initialization, wait for 40ms to pass
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SEND_FS, -- send the function set
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SEND_SD, -- send the display ON/OFF control
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SEND_CD, -- send a clear
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SEND_ES, -- send entry mode set
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SEND_SA, -- send the starting address
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PAUSE, -- wait for 1.52ms
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COUNT, -- wait and toggle lcd_en
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DONE); -- initialization done
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-- signals
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signal init_done : STD_LOGIC := '0'; -- 1 when initialization done, else 0
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signal cur_state : display_state := INIT; -- cur_state register
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signal next_state : display_state := INIT; -- next_state register
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signal ret_state : display_state := INIT; -- ret_state register
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signal next_ret_state : display_state := INIT; -- next_ret_state register
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signal cur_counter : unsigned(NBITS-1 downto 0) := (others => '0'); -- n bit counter signal
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signal next_counter : unsigned(NBITS-1 downto 0) := (others => '0');
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signal ret_counter : unsigned(NBITS-1 downto 0) := (others => '0'); -- n bit counter signal
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signal next_ret_counter : unsigned(NBITS-1 downto 0) := (others => '0');
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signal next_lcd_db : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); -- next lcd databus
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signal next_lcd_en : STD_LOGIC := '0'; -- next lcd enable
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signal next_lcd_rw : STD_LOGIC := '0'; -- next lcd read/write
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signal next_lcd_rs : STD_LOGIC := '0'; -- next lcd register select
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signal cur_lcd_db : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); -- next lcd databus
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signal cur_lcd_en : STD_LOGIC := '0'; -- next lcd enable
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signal cur_lcd_rw : STD_LOGIC := '0'; -- next lcd read/write
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signal cur_lcd_rs : STD_LOGIC := '0'; -- next lcd register select
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-- constants
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constant INIT_COUNT : natural := clk_freq / (1000000 / wait_40000us); -- number of clock cycles for 40us
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constant PAUSE_COUNT : natural := clk_freq / (1000000 / wait_37us); -- number of clock cycles for 37us
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constant CLEAR_DISPLAY_COUNT : natural := clk_freq / (1000000 / wait_1520us); -- number of clock cycles for 1.52ms
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begin
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-- purpose : state register
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-- type : sequential
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-- inputs : clk, reset, next_state
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-- outputs : cur_state
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REGS: process (clk, reset) is
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begin
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if(reset = '1') then -- asynchronous reset
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cur_state <= INIT;
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ret_state <= INIT;
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cur_counter <= (others => '0');
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ret_counter <= (others => '0');
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cur_lcd_db <= (others => '0');
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cur_lcd_en <= '0';
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cur_lcd_rw <= '0';
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cur_lcd_rs <= '0';
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elsif rising_edge(clk) then -- synchronous on clk
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cur_state <= next_state;
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ret_state <= next_ret_state;
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cur_counter <= next_counter;
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ret_counter <= next_ret_counter;
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cur_lcd_db <= next_lcd_db;
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cur_lcd_en <= next_lcd_en;
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cur_lcd_rw <= next_lcd_rw;
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cur_lcd_rs <= next_lcd_rs;
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end if;
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end process REGS;
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-- purpose : Finite state machine next state logic
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-- type : sequential
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-- inputs : clk, cur_state
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-- outputs : none
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NSL: process(clk, cur_state, cur_counter, cur_lcd_db, cur_lcd_en, cur_lcd_rw, cur_lcd_rs, ret_state, ret_counter) is
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begin
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next_state <= cur_state; -- state stays the same
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next_counter <= cur_counter + 1; -- increment counter
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next_lcd_db <= cur_lcd_db;
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next_lcd_en <= cur_lcd_en;
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next_lcd_rw <= cur_lcd_rw;
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next_lcd_rs <= cur_lcd_rs;
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next_ret_state <= ret_state;
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next_ret_counter <= ret_counter;
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case cur_state is -- switch on current state
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when INIT =>
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next_lcd_db <= "00000000";
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next_lcd_en <= '0';
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next_lcd_rw <= '0';
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next_lcd_rs <= '0';
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next_counter <= (others => '0');
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next_ret_state <= SEND_FS;
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next_ret_counter <= to_unsigned(INIT_COUNT,NBITS);
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next_state <= COUNT;
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when SEND_FS =>
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next_lcd_db <= "00110000";
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next_lcd_en <= '0';
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next_lcd_rw <= '0';
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next_lcd_rs <= '0';
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next_counter <= (others => '0');
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next_ret_state <= SEND_SD;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= COUNT;
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when SEND_SD =>
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next_lcd_db <= "00001111";
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next_lcd_en <= '0';
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next_lcd_rw <= '0';
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next_lcd_rs <= '0';
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next_counter <= (others => '0');
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next_ret_state <= SEND_CD;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= COUNT;
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when SEND_CD =>
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next_lcd_db <= "00000001";
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next_lcd_en <= '0';
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next_lcd_rw <= '0';
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next_lcd_rs <= '0';
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next_counter <= (others => '0');
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next_ret_state <= PAUSE;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= PAUSE;
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when PAUSE =>
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next_lcd_db <= "00000000";
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next_lcd_en <= '0';
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next_lcd_rw <= '0';
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next_lcd_rs <= '0';
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next_counter <= (others => '0');
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next_ret_state <= SEND_ES;
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next_ret_counter <= to_unsigned(CLEAR_DISPLAY_COUNT,NBITS);
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next_state <= COUNT;
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when SEND_ES =>
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next_lcd_db <= "00000110";
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next_lcd_en <= '0';
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next_lcd_rw <= '0';
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next_lcd_rs <= '0';
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next_counter <= (others => '0');
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next_ret_state <= SEND_SA;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= COUNT;
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when SEND_SA =>
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next_lcd_db <= "10000000";
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next_lcd_en <= '0';
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next_lcd_rw <= '0';
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next_lcd_rs <= '0';
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next_counter <= (others => '0');
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next_ret_state <= DONE;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= COUNT;
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when COUNT =>
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if(cur_counter >= ret_counter) then
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next_state <= ret_state;
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next_lcd_en <= '1';
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end if;
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when DONE =>
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next_lcd_db <= "10000000";
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next_lcd_en <= '0';
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next_lcd_rw <= '0';
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next_lcd_rs <= '0';
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init_done <= '1';
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when others => null; -- do nothing, if we are in a different state
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end case;
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end process NSL;
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-- Output logic
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lcd_db <= cur_lcd_db;
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lcd_en <= cur_lcd_en;
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lcd_rw <= cur_lcd_rw;
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lcd_rs <= cur_lcd_rs;
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end Behavioral;
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