vhdl-yasg
YASG is yet another signal generator, written in vhdl. It uses Direct Digital Synthesis (DDS) for signal generation. The hardware used will be a Xilinx Spartan-3AN eval board which brings a 12bit analog to digital converter. The boards rotary encoder is used as primary input (choosing signal form and frequency) and the 16x2 LC-Display as optical output.
Used hardware
- Xilinx Spartan-3AN Eval Board
Used software
- Xilinx
- Git
- LibreOffice
- VIM