91 lines
4.0 KiB
VHDL
91 lines
4.0 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project: YASG (Yet another signal generator)
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-- Project Page: https://github.com/id101010/vhdl-yasg/
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-- Authors: Aaron Schmocker & Timo Lang
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-- License: GPL v3
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-- Create Date: 11:09:53 05/16/2016
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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use work.helpers.all;
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entity dds is
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Generic (clk_freq: natural:= 50000000;
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freq_res: natural:=17; -- width of frequency input (log2(max_freq))
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adc_res: natural:=12; -- width of the ouput signal (=adc resolution)
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acc_res: natural:=32; -- width of the phase accumulator
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phase_res: natural:=10); -- effective phase resolution for sin lookup table
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Port ( clk : in STD_LOGIC;
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freq : in unsigned (freq_res-1 downto 0);
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form : in unsigned (1 downto 0);
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amp : out unsigned (adc_res-1 downto 0));
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end dds;
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architecture Behavioral of dds is
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signal m, idx : unsigned(acc_res -1 downto 0):= (others => '0');
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signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0');
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signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0);
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type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0);
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--type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
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function gen_sin_wave return storage is
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variable temp : storage;
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begin
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forLoop: for i in 0 to temp'high loop
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temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1);
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--temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1) + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);
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end loop;
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return temp;
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end function gen_sin_wave;
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constant sin_wave : storage := gen_sin_wave;
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begin
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-- m = fout*(2^n)/fclk = fout*((2^n)*(2^k)/fclk)/(2^k) with k=ceil(log2(fclk)), n=acc_res
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m <= resize( (resize(freq,64)
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*
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(shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq))
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/to_unsigned(2**log2_int(clk_freq),64),acc_res);
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amp_rect <= to_unsigned(0,adc_res) when idx(acc_res-1)='0' else
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to_unsigned((2**adc_res)-1,adc_res);
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amp_saw <= idx(acc_res -1 downto acc_res - adc_res);
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amp_tria <= idx(acc_res -2 downto acc_res - adc_res) & "0"
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when idx(acc_res-1)='0' else
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((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res) & "0");
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idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
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--amp_sin <= sin_wave(to_integer(idx_phase));
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amp_sin <= to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else
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to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="01" else
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to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="10" else
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to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0)));
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amp <= to_unsigned(0,adc_res) when freq = to_unsigned(0,freq_res) else
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amp_rect when form = "00" else
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amp_saw when form ="01" else
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amp_tria when form = "10" else
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amp_sin;
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P1: process(clk)
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begin
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if(rising_edge(clk)) then
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idx <= (idx+m);
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end if;
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end process P1;
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end Behavioral;
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