97 lines
2.3 KiB
VHDL
97 lines
2.3 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project: YASG (Yet another signal generator)
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-- Project Page: https://github.com/id101010/vhdl-yasg/
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-- Authors: Aaron Schmocker & Timo Lang
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-- License: GPL v3
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-- Create Date: 20:08:51 06/06/2016
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY controller_tb IS
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END controller_tb;
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ARCHITECTURE behavior OF controller_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT controller
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PORT(
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clk : IN std_logic;
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rst : IN std_logic;
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enc_updown : IN std_logic;
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enc_ce : IN std_logic;
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enc_btn : IN std_logic;
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enc_err : IN std_logic;
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lcd_busy : IN std_logic;
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lcd_data : OUT unsigned(7 downto 0);
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lcd_newchar : OUT std_logic;
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freq_out : OUT unsigned(16 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal enc_updown : std_logic := '0';
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signal enc_ce : std_logic := '0';
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signal enc_btn : std_logic := '0';
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signal enc_err : std_logic := '0';
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signal lcd_busy : std_logic := '0';
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--Outputs
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signal lcd_data : unsigned(7 downto 0);
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signal lcd_newchar : std_logic;
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signal freq_out : unsigned(16 downto 0);
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: controller PORT MAP (
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clk => clk,
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rst => rst,
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enc_updown => enc_updown,
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enc_ce => enc_ce,
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enc_btn => enc_btn,
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enc_err => enc_err,
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lcd_busy => lcd_busy,
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lcd_data => lcd_data,
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lcd_newchar => lcd_newchar,
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freq_out => freq_out
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clk_period*10;
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rst<= '0';
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lcd_busy <= '0';
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-- insert stimulus here
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wait;
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end process;
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END;
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