14 lines
472 B
Markdown
14 lines
472 B
Markdown
# vhdl-yasg
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YASG is yet another signal generator, written in vhdl. It uses Direct Digital Synthesis (DDS) for signal generation.
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The hardware used will be a Xilinx Spartan-3AN eval board which brings a 12bit analog to digital converter. The boards rotary encoder is used as primary input (choosing signal form and frequency) and
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the 16x2 LC-Display as optical output.
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## Used hardware
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- Xilinx Spartan-3AN Eval Board
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## Used software
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- Xilinx
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- Git
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- LibreOffice
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- VIM
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