98 lines
2.8 KiB
VHDL
98 lines
2.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project: YASG (Yet another signal generator)
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-- Project Page: https://github.com/id101010/vhdl-yasg/
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-- Authors: Aaron Schmocker & Timo Lang
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-- License: GPL v3
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-- Create Date: 19:07:22 05/23/2016
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity rotary_dec is
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Port ( clk : in std_logic; -- Systemtakt
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A : in std_logic; -- Spur A
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B : in std_logic; -- Spur B
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btn : in std_logic; -- Button Input
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btn_deb : out std_logic; -- Button entprellt
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enc_right: out std_logic; -- Zaehlrichtung
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enc_ce : out std_logic); -- Clock Enable
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end rotary_dec;
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architecture Behavioral of rotary_dec is
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signal a_old, b_old: std_logic := '0';
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signal a_debounced_reg, a_debounced_next, b_debounced_reg, b_debounced_next : std_logic := '0';
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signal btn_reg, btn_next: std_logic :='0';
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signal counter_a_reg, counter_a_next,
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counter_b_reg, counter_b_next,
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counter_btn_reg, counter_btn_next: unsigned(23 downto 0) := (others => '0');
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constant count_max: unsigned(23 downto 0) := to_unsigned(500000,24); --10ms
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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counter_a_reg <= counter_a_next;
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counter_b_reg <= counter_b_next;
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counter_btn_reg <= counter_btn_next;
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a_debounced_reg <= a_debounced_next;
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b_debounced_reg <= b_debounced_next;
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a_old <= a_debounced_reg;
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b_old <= b_debounced_reg;
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btn_reg <= btn_next;
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end if;
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end process;
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btn_deb <= btn_reg;
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process(A,B, a_debounced_reg, b_debounced_reg, counter_a_reg, counter_b_reg, btn_reg, btn, counter_btn_reg)
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begin
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if(A /= a_debounced_reg and counter_a_reg > count_max) then
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a_debounced_next <= A;
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counter_a_next <= (others => '0');
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else
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a_debounced_next <= a_debounced_reg;
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counter_a_next <= counter_a_reg + 1;
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end if;
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if(B /= b_debounced_reg and counter_b_reg > count_max) then
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b_debounced_next <= B;
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counter_b_next <= (others => '0');
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else
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b_debounced_next <= b_debounced_reg;
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counter_b_next <= counter_b_reg + 1;
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end if;
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if(btn /= btn_reg and counter_btn_reg > count_max) then
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btn_next <= btn;
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counter_btn_next <= (others => '0');
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else
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btn_next <= btn_reg;
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counter_btn_next <= counter_btn_reg + 1;
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end if;
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end process;
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-- Dekodierung der Ausgaenge
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process(a_debounced_reg, b_debounced_reg, a_old, b_old)
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variable state: std_logic_vector(3 downto 0);
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begin
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state := a_debounced_reg & b_debounced_reg & a_old & b_old;
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case state is
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when "0001" => enc_right <= '0'; enc_ce <= '1';
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when "0010" => enc_right <= '1'; enc_ce <= '1';
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when others => enc_right <= '0'; enc_ce <= '0';
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end case;
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end process;
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end Behavioral;
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