91 lines
2.1 KiB
VHDL
91 lines
2.1 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project: YASG (Yet another signal generator)
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-- Project Page: https://github.com/id101010/vhdl-yasg/
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-- Authors: Aaron Schmocker & Timo Lang
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-- License: GPL v3
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-- Create Date: 21:11:41 05/16/2016
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----------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY lcd_driver_tb IS
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END lcd_driver_tb;
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ARCHITECTURE behavior OF lcd_driver_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT lcd_driver
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PORT(
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clk : IN std_logic;
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reset : IN std_logic;
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data : IN std_logic_vector(7 downto 0);
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new_character : IN std_logic;
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new_pos : IN std_logic;
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lcd_db : OUT std_logic_vector(7 downto 0);
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lcd_en : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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signal data : std_logic_vector(7 downto 0) := (others => '0');
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signal new_character : std_logic := '0';
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signal new_pos : std_logic := '0';
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signal auto_incr_cursor : std_logic := '0';
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--Outputs
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signal lcd_db : std_logic_vector(7 downto 0);
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signal lcd_en : std_logic;
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signal lcd_rw : std_logic;
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signal lcd_rs : std_logic;
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-- Clock period definitions
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constant clk_period : time := 20 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: lcd_driver PORT MAP (
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clk => clk,
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reset => reset,
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data => data,
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new_character => new_character,
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new_pos => new_pos,
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lcd_db => lcd_db,
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lcd_en => lcd_en
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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reset <= '1';
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wait for 100 ns; -- hold reset state for 100 ns.
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reset <= '0';
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-- Apply Data
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--data = ''
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wait for clk_period*10;
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-- insert stimulus here
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wait;
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end process;
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END;
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