98 lines
2.2 KiB
VHDL
98 lines
2.2 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project: YASG (Yet another signal generator)
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-- Project Page: https://github.com/id101010/vhdl-yasg/
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-- Authors: Aaron Schmocker & Timo Lang
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-- License: GPL v3
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-- Create Date: 11:35:57 05/16/2016
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY dds_tb IS
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END dds_tb;
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ARCHITECTURE behavior OF dds_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT dds
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PORT(
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clk : IN std_logic;
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freq : IN unsigned(16 downto 0);
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form : IN unsigned(1 downto 0);
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amp : OUT unsigned(11 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal freq : unsigned(16 downto 0) := (others => '0');
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signal form : unsigned(1 downto 0) := (others => '0');
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--Outputs
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signal amp : unsigned(11 downto 0);
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-- Clock period definitions
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constant clk_period : time := 20 ns; --50mhz
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: dds PORT MAP (
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clk => clk,
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freq => freq,
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form => form,
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amp => amp
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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form <= "00";
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freq <= to_unsigned(50000,17);
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wait for 40 us;
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freq <= to_unsigned(100000,17);
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wait for 20 us;
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form <= "01";
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freq <= to_unsigned(50000,17);
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wait for 40 us;
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freq <= to_unsigned(100000,17);
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wait for 20 us;
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form <= "10";
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freq <= to_unsigned(50000,17);
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wait for 40 us;
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freq <= to_unsigned(100000,17);
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wait for 20 us;
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form <= "11";
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freq <= to_unsigned(50000,17);
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wait for 40 us;
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freq <= to_unsigned(100000,17);
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wait for 20 us;
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wait;
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end process;
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END;
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