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Added screenshots, modified testbench for lcd driver

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id101010
2016-06-19 17:45:45 +02:00
parent 657a3e96a2
commit f7cbd02e6e
4 changed files with 25 additions and 8 deletions
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27
lcd_driver_tb.vhd
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@@ -19,6 +19,7 @@ ARCHITECTURE behavior OF lcd_driver_tb IS
COMPONENT lcd_driver COMPONENT lcd_driver
PORT( PORT(
clk : IN std_logic; clk : IN std_logic;
busy : out STD_LOGIC;
reset : IN std_logic; reset : IN std_logic;
data : IN std_logic_vector(7 downto 0); data : IN std_logic_vector(7 downto 0);
new_character : IN std_logic; new_character : IN std_logic;
@@ -42,6 +43,7 @@ ARCHITECTURE behavior OF lcd_driver_tb IS
signal lcd_en : std_logic; signal lcd_en : std_logic;
signal lcd_rw : std_logic; signal lcd_rw : std_logic;
signal lcd_rs : std_logic; signal lcd_rs : std_logic;
signal busy : std_logic;
-- Clock period definitions -- Clock period definitions
constant clk_period : time := 20 ns; constant clk_period : time := 20 ns;
@@ -56,7 +58,8 @@ BEGIN
new_character => new_character, new_character => new_character,
new_pos => new_pos, new_pos => new_pos,
lcd_db => lcd_db, lcd_db => lcd_db,
lcd_en => lcd_en lcd_en => lcd_en,
busy => busy
); );
-- Clock process definitions -- Clock process definitions
@@ -77,12 +80,26 @@ BEGIN
wait for 100 ns; -- hold reset state for 100 ns. wait for 100 ns; -- hold reset state for 100 ns.
reset <= '0'; reset <= '0';
-- Apply Data wait for 50ms;
--data = ''
wait for clk_period*10;
-- insert stimulus here -- test sending character
data <= "11111111";
new_character <= '1';
new_pos <= '0';
wait until busy = '0';
-- test sending character
data <= "10101010";
new_character <= '0';
new_pos <= '1';
wait until busy = '0';
data <= "00000000";
new_character <= '0';
new_pos <= '0';
wait; wait;
end process; end process;

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4
yasg.xise
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@@ -84,8 +84,8 @@
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/> <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/toplevel" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/lcd_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.toplevel" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.lcd_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>