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Improved lcd driver testbench, added screenshot of data sending

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This commit is contained in:
id101010
2016-06-19 18:14:21 +02:00
parent 411ced7222
commit ed53854a38
6 changed files with 13 additions and 20 deletions
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5
lcd_driver_tb.vhd
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@@ -25,7 +25,8 @@ ARCHITECTURE behavior OF lcd_driver_tb IS
new_character : IN std_logic;
new_pos : IN std_logic;
lcd_db : OUT std_logic_vector(7 downto 0);
lcd_en : OUT std_logic
lcd_en : OUT std_logic;
lcd_rs : OUT std_logic
);
END COMPONENT;
@@ -41,7 +42,6 @@ ARCHITECTURE behavior OF lcd_driver_tb IS
--Outputs
signal lcd_db : std_logic_vector(7 downto 0);
signal lcd_en : std_logic;
signal lcd_rw : std_logic;
signal lcd_rs : std_logic;
signal busy : std_logic;
@@ -59,6 +59,7 @@ BEGIN
new_pos => new_pos,
lcd_db => lcd_db,
lcd_en => lcd_en,
lcd_rs => lcd_rs,
busy => busy
);

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screenshots/LCDTB3.png
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screenshots/LCDTB4.png
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screenshots/LCDTB5.png Normal file
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14
simulate_display_init.wcfg
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@@ -11,7 +11,7 @@
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="19" />
<WVObjectSize size="17" />
<wvobject fp_name="/lcd_driver_tb/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
@@ -40,15 +40,11 @@
<obj_property name="ElementShortName">lcd_db[7:0]</obj_property>
<obj_property name="ObjectShortName">lcd_db[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/lcd_en" type="logic" db_ref_id="1">
<wvobject fp_name="/lcd_driver_tb/uut/lcd_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">lcd_en</obj_property>
<obj_property name="ObjectShortName">lcd_en</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/lcd_rw" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">lcd_rw</obj_property>
<obj_property name="ObjectShortName">lcd_rw</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/lcd_rs" type="logic" db_ref_id="1">
<wvobject fp_name="/lcd_driver_tb/uut/lcd_rs" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">lcd_rs</obj_property>
<obj_property name="ObjectShortName">lcd_rs</obj_property>
</wvobject>
@@ -72,10 +68,6 @@
<obj_property name="ElementShortName">next_ret_state</obj_property>
<obj_property name="ObjectShortName">next_ret_state</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/uut/init_done" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">init_done</obj_property>
<obj_property name="ObjectShortName">init_done</obj_property>
</wvobject>
<wvobject fp_name="/lcd_driver_tb/uut/cur_counter" type="array" db_ref_id="1">
<obj_property name="ElementShortName">cur_counter[20:0]</obj_property>
<obj_property name="ObjectShortName">cur_counter[20:0]</obj_property>

14
yasg.xise
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@@ -16,7 +16,7 @@
<files>
<file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
@@ -51,7 +51,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="rotary.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL">
@@ -59,7 +59,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/>
@@ -71,7 +71,7 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="rotary_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/>
@@ -90,8 +90,8 @@
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/rotary_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.rotary_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/lcd_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.lcd_driver_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -101,7 +101,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|rotary_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|lcd_driver_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>