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Extended controller a bit so that the user can change the digit pos.

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This commit is contained in:
T-moe
2016-06-03 15:20:32 +02:00
parent 17fa0fb90f
commit ecdaaccee5
6 changed files with 152 additions and 119 deletions
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39
controller.sym
View File

@@ -1,28 +1,31 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="controller"> <symbol version="7" name="controller">
<symboltype>BLOCK</symboltype> <symboltype>BLOCK</symboltype>
<timestamp>2016-5-23T16:56:10</timestamp> <timestamp>2016-6-3T12:59:50</timestamp>
<pin polarity="Input" x="0" y="-288" name="clk" /> <pin polarity="Input" x="0" y="-352" name="clk" />
<pin polarity="Input" x="0" y="-224" name="rst" /> <pin polarity="Input" x="0" y="-288" name="rst" />
<pin polarity="Input" x="0" y="-160" name="enc_updown" />
<pin polarity="Input" x="0" y="-96" name="enc_ce" />
<pin polarity="Input" x="0" y="-32" name="enc_err" /> <pin polarity="Input" x="0" y="-32" name="enc_err" />
<pin polarity="Output" x="432" y="-288" name="freq_out(16:0)" /> <pin polarity="Output" x="432" y="-352" name="freq_out(16:0)" />
<pin polarity="Input" x="0" y="-224" name="enc_btn" />
<pin polarity="Input" x="0" y="-96" name="enc_ce" />
<pin polarity="Input" x="0" y="-160" name="enc_updown" />
<graph> <graph>
<rect width="304" x="64" y="-320" height="320" /> <attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="216" y="-392" type="symbol" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="216" y="-328" type="symbol" /> <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin clk" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin clk" /> <line x2="0" y1="-352" y2="-352" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin rst" />
<line x2="0" y1="-288" y2="-288" x1="64" /> <line x2="0" y1="-288" y2="-288" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin rst" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin enc_updown" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin enc_ce" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin enc_err" /> <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin enc_err" />
<line x2="0" y1="-32" y2="-32" x1="64" /> <line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-288" type="pin freq_out(16:0)" /> <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-352" type="pin freq_out(16:0)" />
<rect width="64" x="368" y="-300" height="24" /> <rect width="64" x="368" y="-364" height="24" />
<line x2="432" y1="-288" y2="-288" x1="368" /> <line x2="432" y1="-352" y2="-352" x1="368" />
<rect width="304" x="64" y="-384" height="384" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="76" y="-224" type="pin enc_btn" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin enc_ce" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin enc_updown" />
</graph> </graph>
</symbol> </symbol>

30
controller.vhd
View File

@@ -34,33 +34,57 @@ entity controller is
rst: in STD_LOGIC; rst: in STD_LOGIC;
enc_updown : in STD_LOGIC; enc_updown : in STD_LOGIC;
enc_ce : in STD_LOGIC; enc_ce : in STD_LOGIC;
enc_btn: in STD_LOGIC;
enc_err : in STD_LOGIC; enc_err : in STD_LOGIC;
freq_out : out unsigned (16 downto 0)); freq_out : out unsigned (16 downto 0));
end controller; end controller;
architecture Behavioral of controller is architecture Behavioral of controller is
signal freq_reg, freq_next : unsigned(16 downto 0) := to_unsigned(1000,17); signal freq_reg, freq_next : unsigned(16 downto 0) := to_unsigned(1000,17);
signal digpos_reg, digpos_next : unsigned(2 downto 0) := to_unsigned(0,3);
signal btn_old_reg, btn_old_next : std_logic := '0';
type storage is array (4 downto 0) of unsigned (16 downto 0);
constant bases : storage := (to_unsigned(1,17),to_unsigned(10,17),
to_unsigned(100,17),to_unsigned(1000,17),
to_unsigned(10000,17));
signal digpos_base : unsigned(16 downto 0);
begin begin
proc1: process(clk,rst) proc1: process(clk,rst)
begin begin
if(rst='1') then if(rst='1') then
freq_reg <= to_unsigned(1000,17); freq_reg <= to_unsigned(1000,17);
digpos_reg <= to_unsigned(0,3);
btn_old_reg <= '0';
elsif(rising_edge(clk)) then elsif(rising_edge(clk)) then
freq_reg <= freq_next; freq_reg <= freq_next;
digpos_reg <= digpos_next;
btn_old_reg <= btn_old_next;
end if; end if;
end process proc1; end process proc1;
freq_out <= freq_reg; freq_out <= freq_reg;
digpos_base <= bases(to_integer(digpos_reg));
proc2: process(freq_reg,enc_updown,enc_ce,enc_err) proc2: process(freq_reg,enc_updown,enc_ce,enc_err,enc_btn,digpos_reg,digpos_base,btn_old_reg)
begin begin
freq_next <= freq_reg; freq_next <= freq_reg;
digpos_next <= digpos_reg;
btn_old_next <= enc_btn;
if(enc_ce='1' and enc_err='0') then if(enc_ce='1' and enc_err='0') then
if(enc_updown='1') then if(enc_updown='1') then
freq_next <= freq_reg + 1; freq_next <= freq_reg + digpos_base;
else else
freq_next <= freq_reg - 1; freq_next <= freq_reg - digpos_base;
end if;
elsif(enc_btn ='1' and btn_old_reg='0') then
if(digpos_reg = to_unsigned(4,3)) then
digpos_next <= to_unsigned(0,3);
else
digpos_next <= digpos_reg + 1;
end if; end if;
end if; end if;

4
io.ucf
View File

@@ -19,4 +19,6 @@ NET "SW0" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ; NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ;
NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP; NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP; NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN;

106
toplevel.sch
View File

@@ -6,7 +6,6 @@
<trait edittrait="all:0" /> <trait edittrait="all:0" />
</attr> </attr>
<netlist> <netlist>
<signal name="XLXN_67" />
<signal name="FORM(1:0)" /> <signal name="FORM(1:0)" />
<signal name="FORM(0)" /> <signal name="FORM(0)" />
<signal name="FORM(1)" /> <signal name="FORM(1)" />
@@ -29,9 +28,10 @@
<signal name="XLXN_63" /> <signal name="XLXN_63" />
<signal name="XLXN_64" /> <signal name="XLXN_64" />
<signal name="XLXN_65" /> <signal name="XLXN_65" />
<signal name="XLXN_66" /> <signal name="XLXN_68" />
<signal name="ROT_A" /> <signal name="ROT_A" />
<signal name="ROT_B" /> <signal name="ROT_B" />
<signal name="ROT_CENTER" />
<port polarity="Input" name="CLK_50MHZ" /> <port polarity="Input" name="CLK_50MHZ" />
<port polarity="Output" name="SPI_SCK" /> <port polarity="Output" name="SPI_SCK" />
<port polarity="Output" name="DAC_CS" /> <port polarity="Output" name="DAC_CS" />
@@ -46,6 +46,7 @@
<port polarity="Input" name="SW1" /> <port polarity="Input" name="SW1" />
<port polarity="Input" name="ROT_A" /> <port polarity="Input" name="ROT_A" />
<port polarity="Input" name="ROT_B" /> <port polarity="Input" name="ROT_B" />
<port polarity="Input" name="ROT_CENTER" />
<blockdef name="spi_driver"> <blockdef name="spi_driver">
<timestamp>2016-5-20T8:33:2</timestamp> <timestamp>2016-5-20T8:33:2</timestamp>
<rect width="256" x="64" y="-192" height="192" /> <rect width="256" x="64" y="-192" height="192" />
@@ -92,15 +93,16 @@
<line x2="32" y1="-64" y2="-64" x1="96" /> <line x2="32" y1="-64" y2="-64" x1="96" />
</blockdef> </blockdef>
<blockdef name="controller"> <blockdef name="controller">
<timestamp>2016-5-23T16:56:10</timestamp> <timestamp>2016-6-3T12:59:50</timestamp>
<rect width="304" x="64" y="-320" height="320" /> <line x2="0" y1="-352" y2="-352" x1="64" />
<line x2="0" y1="-288" y2="-288" x1="64" /> <line x2="0" y1="-288" y2="-288" x1="64" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" /> <line x2="0" y1="-32" y2="-32" x1="64" />
<rect width="64" x="368" y="-300" height="24" /> <rect width="64" x="368" y="-364" height="24" />
<line x2="432" y1="-288" y2="-288" x1="368" /> <line x2="432" y1="-352" y2="-352" x1="368" />
<rect width="304" x="64" y="-384" height="384" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
</blockdef> </blockdef>
<blockdef name="rotary_dec"> <blockdef name="rotary_dec">
<timestamp>2016-5-23T16:56:27</timestamp> <timestamp>2016-5-23T16:56:27</timestamp>
@@ -166,11 +168,12 @@
</block> </block>
<block symbolname="controller" name="XLXI_42"> <block symbolname="controller" name="XLXI_42">
<blockpin signalname="CLK_50MHZ" name="clk" /> <blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="XLXN_66" name="rst" /> <blockpin signalname="XLXN_68" name="rst" />
<blockpin signalname="XLXN_65" name="enc_updown" />
<blockpin signalname="XLXN_64" name="enc_ce" />
<blockpin signalname="XLXN_63" name="enc_err" /> <blockpin signalname="XLXN_63" name="enc_err" />
<blockpin signalname="FREQ(16:0)" name="freq_out(16:0)" /> <blockpin signalname="FREQ(16:0)" name="freq_out(16:0)" />
<blockpin signalname="ROT_CENTER" name="enc_btn" />
<blockpin signalname="XLXN_64" name="enc_ce" />
<blockpin signalname="XLXN_65" name="enc_updown" />
</block> </block>
<block symbolname="rotary_dec" name="XLXI_43"> <block symbolname="rotary_dec" name="XLXI_43">
<blockpin signalname="CLK_50MHZ" name="clk" /> <blockpin signalname="CLK_50MHZ" name="clk" />
@@ -181,7 +184,7 @@
<blockpin signalname="XLXN_63" name="error" /> <blockpin signalname="XLXN_63" name="error" />
</block> </block>
<block symbolname="gnd" name="XLXI_44"> <block symbolname="gnd" name="XLXI_44">
<blockpin signalname="XLXN_66" name="G" /> <blockpin signalname="XLXN_68" name="G" />
</block> </block>
</netlist> </netlist>
<sheet sheetnum="1" width="5440" height="3520"> <sheet sheetnum="1" width="5440" height="3520">
@@ -242,12 +245,10 @@
<wire x2="3616" y1="1312" y2="1312" x1="3264" /> <wire x2="3616" y1="1312" y2="1312" x1="3264" />
</branch> </branch>
<branch name="FREQ(16:0)"> <branch name="FREQ(16:0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2075" y="1424" type="branch" /> <attrtext style="alignment:SOFT-LEFT;fontsize:28;fontname:Arial" attrname="Name" x="2075" y="1424" type="branch" />
<wire x2="1904" y1="1152" y2="1152" x1="1664" /> <wire x2="1904" y1="1088" y2="1088" x1="1664" />
<wire x2="1904" y1="1152" y2="1344" x1="1904" /> <wire x2="1904" y1="1088" y2="1424" x1="1904" />
<wire x2="1904" y1="1344" y2="1424" x1="1904" /> <wire x2="2256" y1="1424" y2="1424" x1="1904" />
<wire x2="2075" y1="1424" y2="1424" x1="1904" />
<wire x2="2256" y1="1424" y2="1424" x1="2075" />
</branch> </branch>
<instance x="3392" y="1168" name="XLXI_14" orien="R0" /> <instance x="3392" y="1168" name="XLXI_14" orien="R0" />
<branch name="J18_IO4"> <branch name="J18_IO4">
@@ -294,39 +295,14 @@
<wire x2="1600" y1="1568" y2="1568" x1="1504" /> <wire x2="1600" y1="1568" y2="1568" x1="1504" />
</branch> </branch>
<instance x="1600" y="1680" name="XLXI_27" orien="R0" /> <instance x="1600" y="1680" name="XLXI_27" orien="R0" />
<instance x="1232" y="1440" name="XLXI_42" orien="R0">
</instance>
<instance x="768" y="1440" name="XLXI_43" orien="R0">
</instance>
<branch name="XLXN_63"> <branch name="XLXN_63">
<wire x2="1232" y1="1408" y2="1408" x1="1152" /> <wire x2="1232" y1="1408" y2="1408" x1="912" />
</branch> </branch>
<branch name="XLXN_64"> <branch name="XLXN_64">
<wire x2="1232" y1="1344" y2="1344" x1="1152" /> <wire x2="1232" y1="1344" y2="1344" x1="912" />
</branch> </branch>
<branch name="XLXN_65"> <branch name="XLXN_65">
<wire x2="1232" y1="1280" y2="1280" x1="1152" /> <wire x2="1232" y1="1280" y2="1280" x1="912" />
</branch>
<instance x="1072" y="1200" name="XLXI_44" orien="R0" />
<branch name="XLXN_66">
<wire x2="1136" y1="1056" y2="1072" x1="1136" />
<wire x2="1184" y1="1056" y2="1056" x1="1136" />
<wire x2="1184" y1="1056" y2="1216" x1="1184" />
<wire x2="1232" y1="1216" y2="1216" x1="1184" />
</branch>
<branch name="CLK_50MHZ">
<wire x2="1216" y1="976" y2="976" x1="1136" />
<wire x2="1216" y1="976" y2="1152" x1="1216" />
<wire x2="1232" y1="1152" y2="1152" x1="1216" />
</branch>
<branch name="ROT_A">
<wire x2="768" y1="1344" y2="1344" x1="736" />
</branch>
<branch name="ROT_B">
<wire x2="768" y1="1408" y2="1408" x1="736" />
</branch>
<branch name="CLK_50MHZ">
<wire x2="768" y1="1280" y2="1280" x1="736" />
</branch> </branch>
<iomarker fontsize="28" x="2224" y="1360" name="CLK_50MHZ" orien="R180" /> <iomarker fontsize="28" x="2224" y="1360" name="CLK_50MHZ" orien="R180" />
<iomarker fontsize="28" x="3392" y="1216" name="SPI_SCK" orien="R0" /> <iomarker fontsize="28" x="3392" y="1216" name="SPI_SCK" orien="R0" />
@@ -341,9 +317,37 @@
<iomarker fontsize="28" x="1872" y="1648" name="LED0" orien="R0" /> <iomarker fontsize="28" x="1872" y="1648" name="LED0" orien="R0" />
<iomarker fontsize="28" x="1504" y="1568" name="SW1" orien="R180" /> <iomarker fontsize="28" x="1504" y="1568" name="SW1" orien="R180" />
<iomarker fontsize="28" x="1504" y="1504" name="SW0" orien="R180" /> <iomarker fontsize="28" x="1504" y="1504" name="SW0" orien="R180" />
<iomarker fontsize="28" x="1136" y="976" name="CLK_50MHZ" orien="R180" /> <instance x="1232" y="1440" name="XLXI_42" orien="R0">
<iomarker fontsize="28" x="736" y="1344" name="ROT_A" orien="R180" /> </instance>
<iomarker fontsize="28" x="736" y="1408" name="ROT_B" orien="R180" /> <branch name="CLK_50MHZ">
<iomarker fontsize="28" x="736" y="1280" name="CLK_50MHZ" orien="R180" /> <wire x2="1216" y1="880" y2="880" x1="1152" />
<wire x2="1216" y1="880" y2="1088" x1="1216" />
<wire x2="1232" y1="1088" y2="1088" x1="1216" />
</branch>
<iomarker fontsize="28" x="1152" y="880" name="CLK_50MHZ" orien="R180" />
<instance x="528" y="1440" name="XLXI_43" orien="R0">
</instance>
<branch name="ROT_A">
<wire x2="528" y1="1344" y2="1344" x1="496" />
</branch>
<branch name="ROT_B">
<wire x2="528" y1="1408" y2="1408" x1="496" />
</branch>
<branch name="CLK_50MHZ">
<wire x2="528" y1="1280" y2="1280" x1="496" />
</branch>
<iomarker fontsize="28" x="496" y="1344" name="ROT_A" orien="R180" />
<iomarker fontsize="28" x="496" y="1408" name="ROT_B" orien="R180" />
<iomarker fontsize="28" x="496" y="1280" name="CLK_50MHZ" orien="R180" />
<instance x="1040" y="1120" name="XLXI_44" orien="R0" />
<branch name="XLXN_68">
<wire x2="1184" y1="992" y2="992" x1="1104" />
<wire x2="1184" y1="992" y2="1152" x1="1184" />
<wire x2="1232" y1="1152" y2="1152" x1="1184" />
</branch>
<branch name="ROT_CENTER">
<wire x2="1232" y1="1216" y2="1216" x1="1200" />
</branch>
<iomarker fontsize="28" x="1200" y="1216" name="ROT_CENTER" orien="R180" />
</sheet> </sheet>
</drawing> </drawing>

74
yasg.gise
View File

@@ -63,7 +63,9 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="dds_pad.csv" xil_pn:subbranch="Par"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="dds_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="dds_pad.txt" xil_pn:subbranch="Par"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="dds_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_summary.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_summary.html"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="dds_tb_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="dds_tb_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="dds_tb_isim_beh.wdb"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_stx_beh.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_stx_beh.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_vhdl.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="dds_xst.xrpt"/> <file xil_pn:fileType="FILE_XRPT" xil_pn:name="dds_xst.xrpt"/>
@@ -92,9 +94,7 @@
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_envsettings.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_envsettings.html"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_isim_beh.exe"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_summary.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_driver_tb_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_tb_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_tb_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="spi_driver_tb_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_driver_xst.xrpt"/> <file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_driver_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="toplevel.bgn" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="toplevel.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="toplevel.bit" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="toplevel.bit" xil_pn:subbranch="FPGAConfiguration"/>
@@ -135,6 +135,7 @@
<file xil_pn:fileType="FILE_HTML" xil_pn:name="toplevel_summary.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="toplevel_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="toplevel_summary.xml"/> <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="toplevel_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="toplevel_usage.xml"/> <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="toplevel_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="toplevel_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_xst.xrpt"/> <file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_xst.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/> <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
@@ -149,38 +150,37 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492912" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463492912"> <transform xil_pn:end_ts="1464953958" xil_pn:in_ck="7359381923225456452" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1464953958">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="controller.vhd"/>
<outfile xil_pn:name="dds.vhd"/> <outfile xil_pn:name="dds.vhd"/>
<outfile xil_pn:name="dds_tb.vhd"/> <outfile xil_pn:name="dds_tb.vhd"/>
<outfile xil_pn:name="helpers.vhd"/> <outfile xil_pn:name="helpers.vhd"/>
<outfile xil_pn:name="lcd_driver.vhd"/> <outfile xil_pn:name="lcd_driver.vhd"/>
<outfile xil_pn:name="rotary.vhd"/>
<outfile xil_pn:name="spi_driver.vhd"/> <outfile xil_pn:name="spi_driver.vhd"/>
<outfile xil_pn:name="spi_driver_tb.vhd"/> <outfile xil_pn:name="spi_driver_tb.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1463508117" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="9076618275249177275" xil_pn:start_ts="1463508117"> <transform xil_pn:end_ts="1464093026" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8944967924106743327" xil_pn:start_ts="1464093026">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463508117" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="983764721944091843" xil_pn:start_ts="1463508117"> <transform xil_pn:end_ts="1464093027" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5140074775533282471" xil_pn:start_ts="1464093026">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492319" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="7922287241511046268" xil_pn:start_ts="1463492319"> <transform xil_pn:end_ts="1464081246" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1464081246">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform> </transform>
<transform xil_pn:end_ts="1463492912" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463492912"> <transform xil_pn:end_ts="1464953958" xil_pn:in_ck="7359381923225456452" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1464953958">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
@@ -188,71 +188,72 @@
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="controller.vhd"/>
<outfile xil_pn:name="dds.vhd"/> <outfile xil_pn:name="dds.vhd"/>
<outfile xil_pn:name="dds_tb.vhd"/> <outfile xil_pn:name="dds_tb.vhd"/>
<outfile xil_pn:name="helpers.vhd"/> <outfile xil_pn:name="helpers.vhd"/>
<outfile xil_pn:name="lcd_driver.vhd"/> <outfile xil_pn:name="lcd_driver.vhd"/>
<outfile xil_pn:name="rotary.vhd"/>
<outfile xil_pn:name="spi_driver.vhd"/> <outfile xil_pn:name="spi_driver.vhd"/>
<outfile xil_pn:name="spi_driver_tb.vhd"/> <outfile xil_pn:name="spi_driver_tb.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1463573880" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6914626614812979269" xil_pn:start_ts="1463573878"> <transform xil_pn:end_ts="1464953960" xil_pn:in_ck="7359381923225456452" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6917596232395121981" xil_pn:start_ts="1464953958">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="dds_tb_beh.prj"/>
<outfile xil_pn:name="dds_tb_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/> <outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/> <outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="spi_driver_tb_beh.prj"/>
<outfile xil_pn:name="spi_driver_tb_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/> <outfile xil_pn:name="xilinxsim.ini"/>
</transform> </transform>
<transform xil_pn:end_ts="1463573880" xil_pn:in_ck="-1222633688712987584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4788567445176171336" xil_pn:start_ts="1463573880"> <transform xil_pn:end_ts="1464954092" xil_pn:in_ck="-1222633688712987584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1464954092">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="dds_tb_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/> <outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="spi_driver_tb_isim_beh.wdb"/>
</transform> </transform>
<transform xil_pn:end_ts="1463732677" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1463732677"> <transform xil_pn:end_ts="1464958322" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1464958322">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1464023169" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1464023167"> <transform xil_pn:end_ts="1464958805" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1464958803">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="toplevel.vhf"/> <outfile xil_pn:name="toplevel.vhf"/>
</transform> </transform>
<transform xil_pn:end_ts="1463733715" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1463733715"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463733715" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1463733715"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463733715" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2239360189155701135" xil_pn:start_ts="1463733715"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2239360189155701135" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463734910" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1463734910"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463733715" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7072966905182239268" xil_pn:start_ts="1463733715"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7072966905182239268" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1464023279" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1464023169"> <transform xil_pn:end_ts="1464959693" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1464959680">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
@@ -272,11 +273,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1464023279" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1464023279"> <transform xil_pn:end_ts="1464958336" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1464958336">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1464023287" xil_pn:in_ck="2169537708537049843" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1464023279"> <transform xil_pn:end_ts="1464959698" xil_pn:in_ck="2169537708537049843" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1464959693">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
@@ -285,12 +286,9 @@
<outfile xil_pn:name="toplevel.ngd"/> <outfile xil_pn:name="toplevel.ngd"/>
<outfile xil_pn:name="toplevel_ngdbuild.xrpt"/> <outfile xil_pn:name="toplevel_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1464023306" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1464023287"> <transform xil_pn:end_ts="1464959705" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1464959698">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="toplevel.pcf"/> <outfile xil_pn:name="toplevel.pcf"/>
<outfile xil_pn:name="toplevel_map.map"/> <outfile xil_pn:name="toplevel_map.map"/>
@@ -301,9 +299,8 @@
<outfile xil_pn:name="toplevel_summary.xml"/> <outfile xil_pn:name="toplevel_summary.xml"/>
<outfile xil_pn:name="toplevel_usage.xml"/> <outfile xil_pn:name="toplevel_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1464023444" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1464023306"> <transform xil_pn:end_ts="1464959723" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1464959705">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="toplevel.ncd"/> <outfile xil_pn:name="toplevel.ncd"/>
@@ -316,7 +313,7 @@
<outfile xil_pn:name="toplevel_pad.txt"/> <outfile xil_pn:name="toplevel_pad.txt"/>
<outfile xil_pn:name="toplevel_par.xrpt"/> <outfile xil_pn:name="toplevel_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1464023466" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1464023444"> <transform xil_pn:end_ts="1464959731" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1464959723">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -328,12 +325,15 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1464023484" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1464023483"> <transform xil_pn:end_ts="1464955208" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1464955207">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1464023444" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1464023434"> <transform xil_pn:end_ts="1464959723" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1464959719">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

18
yasg.xise
View File

@@ -20,42 +20,42 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
</file> </file>
<file xil_pn:name="spi_driver.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="spi_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="spi_driver_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="spi_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="48"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/>
</file> </file>
<file xil_pn:name="toplevel.sch" xil_pn:type="FILE_SCHEMATIC"> <file xil_pn:name="toplevel.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="io.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="io.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="rotary.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="rotary.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
</files> </files>
@@ -82,7 +82,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|spi_driver_tb|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|dds_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>