diff --git a/controller.sym b/controller.sym
index edf28fc..f90185d 100644
--- a/controller.sym
+++ b/controller.sym
@@ -1,28 +1,31 @@
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diff --git a/controller.vhd b/controller.vhd
index 437f611..3f6bcfb 100644
--- a/controller.vhd
+++ b/controller.vhd
@@ -34,33 +34,57 @@ entity controller is
rst: in STD_LOGIC;
enc_updown : in STD_LOGIC;
enc_ce : in STD_LOGIC;
+ enc_btn: in STD_LOGIC;
enc_err : in STD_LOGIC;
freq_out : out unsigned (16 downto 0));
end controller;
architecture Behavioral of controller is
signal freq_reg, freq_next : unsigned(16 downto 0) := to_unsigned(1000,17);
+ signal digpos_reg, digpos_next : unsigned(2 downto 0) := to_unsigned(0,3);
+ signal btn_old_reg, btn_old_next : std_logic := '0';
+
+ type storage is array (4 downto 0) of unsigned (16 downto 0);
+ constant bases : storage := (to_unsigned(1,17),to_unsigned(10,17),
+ to_unsigned(100,17),to_unsigned(1000,17),
+ to_unsigned(10000,17));
+
+ signal digpos_base : unsigned(16 downto 0);
begin
proc1: process(clk,rst)
begin
if(rst='1') then
freq_reg <= to_unsigned(1000,17);
+ digpos_reg <= to_unsigned(0,3);
+ btn_old_reg <= '0';
elsif(rising_edge(clk)) then
freq_reg <= freq_next;
+ digpos_reg <= digpos_next;
+ btn_old_reg <= btn_old_next;
end if;
end process proc1;
freq_out <= freq_reg;
+ digpos_base <= bases(to_integer(digpos_reg));
- proc2: process(freq_reg,enc_updown,enc_ce,enc_err)
+ proc2: process(freq_reg,enc_updown,enc_ce,enc_err,enc_btn,digpos_reg,digpos_base,btn_old_reg)
begin
freq_next <= freq_reg;
+ digpos_next <= digpos_reg;
+ btn_old_next <= enc_btn;
+
if(enc_ce='1' and enc_err='0') then
if(enc_updown='1') then
- freq_next <= freq_reg + 1;
+ freq_next <= freq_reg + digpos_base;
else
- freq_next <= freq_reg - 1;
+ freq_next <= freq_reg - digpos_base;
+ end if;
+ elsif(enc_btn ='1' and btn_old_reg='0') then
+ if(digpos_reg = to_unsigned(4,3)) then
+ digpos_next <= to_unsigned(0,3);
+ else
+ digpos_next <= digpos_reg + 1;
end if;
end if;
diff --git a/io.ucf b/io.ucf
index 24d0206..e441457 100644
--- a/io.ucf
+++ b/io.ucf
@@ -19,4 +19,6 @@ NET "SW0" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ;
NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP;
-NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP;
\ No newline at end of file
+NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN;
+
\ No newline at end of file
diff --git a/toplevel.sch b/toplevel.sch
index c2f21e0..7c324d3 100644
--- a/toplevel.sch
+++ b/toplevel.sch
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diff --git a/yasg.gise b/yasg.gise
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diff --git a/yasg.xise b/yasg.xise
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