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Added some missing generic parameters.

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T-moe
2016-06-19 16:49:07 +02:00
parent f5f862c044
commit d0ab7b7d16
5 changed files with 97 additions and 11 deletions
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dds.vhd
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@@ -15,7 +15,7 @@ use work.helpers.all;
entity dds is
Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz
freq_res: natural:=17; -- width of frequency input (log2(max_freq))
adc_res: natural:=12; -- width of the ouput signal (=adc resolution)
adc_res: natural:=12; -- width of the output signal (=adc resolution)
acc_res: natural:=32; -- width of the phase accumulator
phase_res: natural:=10); -- effective phase resolution for sin lookup table
Port ( clk : in STD_LOGIC; -- Clock input