diff --git a/controller.vhd b/controller.vhd
index 93a393d..7afe203 100644
--- a/controller.vhd
+++ b/controller.vhd
@@ -11,6 +11,7 @@ use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
 entity controller is
+    Generic (freq_res: natural:=17);                 -- width of frequency input (log2(max_freq))
     Port ( clk : in  STD_LOGIC;                      -- Clock Input
            rst: in STD_LOGIC;                        -- High active, async reset
            enc_right : in  STD_LOGIC;                -- Encoder Input: 1= Direction Right, 0 = Direction Left
@@ -21,7 +22,7 @@ entity controller is
            lcd_data: out unsigned(7 downto 0);       -- LCD Output: Data output
            lcd_newchar: out STD_LOGIC;               -- LCD Output: Send a new character to the lcd
            lcd_newpos : out STD_LOGIC;               -- LCD Output: Send a new position/adress to the lcd
-           freq_out : out  unsigned (16 downto 0));  -- Frequency Ouput (Treshould in Hz)
+           freq_out : out  unsigned (freq_res-1 downto 0));  -- Frequency Output (Treshould in Hz)
 end controller;
 
 architecture Behavioral of controller is
@@ -53,7 +54,7 @@ architecture Behavioral of controller is
    signal lcd_newpos_reg,lcd_newpos_next : std_logic := '0';                       -- Register for the LCD Newpos signal
    signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0');     -- Register for the LCD Databus signal
    
-   signal freq_out_reg, freq_out_next : unsigned (16 downto 0) := (others => '0'); -- Register for the frequency ouput (in hz)
+   signal freq_out_reg, freq_out_next : unsigned (16 downto 0) := (others => '0'); -- Register for the frequency output (in hz)
    
    ----------------Constants---------------------------------
   
@@ -153,7 +154,7 @@ begin
                                + resize(digit_reg(2) ,7)* 100
                                + resize(digit_reg(3) ,10) * 1000
                                + resize(digit_reg(4) ,14) * 10000
-                              ,17);
+                              ,freq_res);
                
             
       case state_reg is -- switch on current state
diff --git a/dds.vhd b/dds.vhd
index c03ff9e..298de17 100644
--- a/dds.vhd
+++ b/dds.vhd
@@ -15,7 +15,7 @@ use work.helpers.all;
 entity dds is
     Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz
              freq_res: natural:=17;        -- width of frequency input (log2(max_freq))
-             adc_res: natural:=12;         -- width of the ouput signal (=adc resolution)
+             adc_res: natural:=12;         -- width of the output signal (=adc resolution)
              acc_res: natural:=32;         -- width of the phase accumulator
              phase_res: natural:=10);      -- effective phase resolution for sin lookup table
     Port ( clk : in  STD_LOGIC;                        -- Clock input
diff --git a/rotary.vhd b/rotary.vhd
index b9b5745..f45d718 100644
--- a/rotary.vhd
+++ b/rotary.vhd
@@ -11,6 +11,8 @@ use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
  
 entity rotary_dec is
+    Generic (clk_freq: natural:= 50000000;  -- Clock frequency in hz
+             debounce_time: natural := 10);  -- Debounce time in ms
     Port ( clk      : in std_logic;         -- Clock Input
            A        : in std_logic;         -- Signal A
            B        : in std_logic;         -- Signal B
@@ -30,7 +32,7 @@ signal btn_reg, btn_next: std_logic :='0';  -- Registers for debouncing Button P
 signal counter_a_reg, counter_a_next,       -- Counters to smooth chittering = debounce signals
        counter_b_reg, counter_b_next,
        counter_btn_reg, counter_btn_next: unsigned(23 downto 0) := (others => '0');
-constant count_max: unsigned(23 downto 0) := to_unsigned(500000,24); --Number of cycles during which a signal can't change it's value 50mhz*10ms= 500000 cycles
+constant count_max: unsigned(23 downto 0) := to_unsigned(clk_freq / (1000 / debounce_time),24); --Number of cycles during which a signal can't change it's value 50mhz*10ms= 500000 cycles   
  
 begin
  
diff --git a/rotary_tb.vhd b/rotary_tb.vhd
new file mode 100644
index 0000000..10dac39
--- /dev/null
+++ b/rotary_tb.vhd
@@ -0,0 +1,77 @@
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
+-- Create Date:    13:41:21 06/19/2016
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+ENTITY rotary_tb IS
+END rotary_tb;
+ 
+ARCHITECTURE behavior OF rotary_tb IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT rotary_dec
+    PORT(
+         clk : IN  std_logic;
+         A : IN  std_logic;
+         B : IN  std_logic;
+         btn : IN  std_logic;
+         btn_deb : OUT  std_logic;
+         enc_right : OUT  std_logic;
+         enc_ce : OUT  std_logic
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk : std_logic := '0';
+   signal A : std_logic := '0';
+   signal B : std_logic := '0';
+   signal btn : std_logic := '0';
+
+    --Outputs
+   signal btn_deb : std_logic;
+   signal enc_right : std_logic;
+   signal enc_ce : std_logic;
+
+   -- Clock period definitions
+   constant clk_period : time := 10 ns;
+ 
+BEGIN
+ 
+   -- Instantiate the Unit Under Test (UUT)
+   uut: rotary_dec PORT MAP (
+          clk => clk,
+          A => A,
+          B => B,
+          btn => btn,
+          btn_deb => btn_deb,
+          enc_right => enc_right,
+          enc_ce => enc_ce
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+      clk <= '0';
+      wait for clk_period/2;
+      clk <= '1';
+      wait for clk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin      
+    
+
+      wait;
+   end process;
+
+END;
diff --git a/yasg.xise b/yasg.xise
index 746f432..f94e069 100644
--- a/yasg.xise
+++ b/yasg.xise
@@ -16,7 +16,7 @@
 
   <files>
     <file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
@@ -51,7 +51,7 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="rotary.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL">
@@ -59,7 +59,7 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/>
@@ -70,6 +70,12 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
     </file>
+    <file xil_pn:name="rotary_tb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/>
+    </file>
   </files>
 
   <properties>
@@ -84,8 +90,8 @@
     <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/toplevel" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.toplevel" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/rotary_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.rotary_tb" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@@ -95,7 +101,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|lcd_driver_tb|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|rotary_tb|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>