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Added rotary decoder and simple controller

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This commit is contained in:
T-moe
2016-05-23 19:22:33 +02:00
parent 16b7cc71ee
commit bc78a40708
10 changed files with 409 additions and 143 deletions
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28
controller.sym Normal file
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@@ -0,0 +1,28 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="controller">
<symboltype>BLOCK</symboltype>
<timestamp>2016-5-23T16:56:10</timestamp>
<pin polarity="Input" x="0" y="-288" name="clk" />
<pin polarity="Input" x="0" y="-224" name="rst" />
<pin polarity="Input" x="0" y="-160" name="enc_updown" />
<pin polarity="Input" x="0" y="-96" name="enc_ce" />
<pin polarity="Input" x="0" y="-32" name="enc_err" />
<pin polarity="Output" x="432" y="-288" name="freq_out(16:0)" />
<graph>
<rect width="304" x="64" y="-320" height="320" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="216" y="-328" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin clk" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin rst" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin enc_updown" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin enc_ce" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin enc_err" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-288" type="pin freq_out(16:0)" />
<rect width="64" x="368" y="-300" height="24" />
<line x2="432" y1="-288" y2="-288" x1="368" />
</graph>
</symbol>

70
controller.vhd Normal file
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@@ -0,0 +1,70 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:47:36 05/23/2016
-- Design Name:
-- Module Name: controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity controller is
Port ( clk : in STD_LOGIC;
rst: in STD_LOGIC;
enc_updown : in STD_LOGIC;
enc_ce : in STD_LOGIC;
enc_err : in STD_LOGIC;
freq_out : out unsigned (16 downto 0));
end controller;
architecture Behavioral of controller is
signal freq_reg, freq_next : unsigned(16 downto 0) := to_unsigned(1000,17);
begin
proc1: process(clk,rst)
begin
if(rst='1') then
freq_reg <= to_unsigned(1000,17);
elsif(rising_edge(clk)) then
freq_reg <= freq_next;
end if;
end process proc1;
freq_out <= freq_reg;
proc2: process(freq_reg,enc_updown,enc_ce,enc_err)
begin
freq_next <= freq_reg;
if(enc_ce='1' and enc_err='0') then
if(enc_updown='1') then
freq_next <= freq_reg + 1;
else
freq_next <= freq_reg - 1;
end if;
end if;
end process proc2;
end Behavioral;

2
dds.vhd
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@@ -55,7 +55,7 @@ begin
-- m = fout*(2^n)/fclk -- m = fout*(2^n)/fclk
m <= resize(divide(shift_left(resize(freq,64),acc_res),to_unsigned(clk_freq,64)),m'length); m <= resize(divide(shift_left(resize(freq,64),acc_res),to_unsigned(clk_freq,64)),m'length);
idx_phase <= idx(acc_res -1 downto acc_res - phase_res); idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
amp_rect <= to_unsigned(0,adc_res) when idx_phase(phase_res-1)='0' else amp_rect <= to_unsigned(0,adc_res) when idx_phase(phase_res-1)='0' else
to_unsigned((2**adc_res)-1,adc_res); to_unsigned((2**adc_res)-1,adc_res);

5
io.ucf
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@@ -16,4 +16,7 @@ NET "J18_IO4" LOC = "AB19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8
NET "LED0" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "LED0" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SW0" LOC = "V8" | IOSTANDARD = LVCMOS33 ; NET "SW0" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ; NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ;
NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP;

65
rotary.vhd Normal file
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@@ -0,0 +1,65 @@
-----------------------------------------------------------------------------
--
-- Decoder für Drehgeber
--
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rotary_dec is
Port ( clk : in std_logic; -- Systemtakt
A : in std_logic; -- Spur A
B : in std_logic; -- Spur B
up_down : out std_logic; -- Zaehlrichtung
ce : out std_logic; -- Clock Enable
error : out std_logic); -- illegaler Signalübergang
end rotary_dec;
architecture Behavioral of rotary_dec is
signal a_in, b_in, a_old, b_old: std_logic;
begin
-- Abtastung und Verzoegerung der Quadratursignale
process(clk)
begin
if rising_edge(clk) then
a_old <= a_in;
a_in <= A;
b_old <= b_in;
b_in <= B;
end if;
end process;
-- Dekodierung der Ausgaenge
process(a_in, b_in, a_old, b_old)
variable state: std_logic_vector(3 downto 0);
begin
state := a_in & b_in & a_old & b_old;
case state is
when "0000" => up_down <= '0'; ce <= '0'; error <= '0';
when "0001" => up_down <= '1'; ce <= '1'; error <= '0';
when "0010" => up_down <= '0'; ce <= '1'; error <= '0';
when "0011" => up_down <= '0'; ce <= '0'; error <= '1';
when "0100" => up_down <= '0'; ce <= '1'; error <= '0';
when "0101" => up_down <= '0'; ce <= '0'; error <= '0';
when "0110" => up_down <= '0'; ce <= '0'; error <= '1';
when "0111" => up_down <= '1'; ce <= '1'; error <= '0';
when "1000" => up_down <= '1'; ce <= '1'; error <= '0';
when "1001" => up_down <= '0'; ce <= '0'; error <= '1';
when "1010" => up_down <= '0'; ce <= '0'; error <= '0';
when "1011" => up_down <= '0'; ce <= '1'; error <= '0';
when "1100" => up_down <= '0'; ce <= '0'; error <= '1';
when "1101" => up_down <= '0'; ce <= '1'; error <= '0';
when "1110" => up_down <= '1'; ce <= '1'; error <= '0';
when "1111" => up_down <= '0'; ce <= '0'; error <= '0';
when others => null;
end case;
end process;
end Behavioral;

27
rotary_dec.sym Normal file
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@@ -0,0 +1,27 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="rotary_dec">
<symboltype>BLOCK</symboltype>
<timestamp>2016-5-23T16:56:27</timestamp>
<pin polarity="Input" x="0" y="-160" name="clk" />
<pin polarity="Input" x="0" y="-96" name="A" />
<pin polarity="Input" x="0" y="-32" name="B" />
<pin polarity="Output" x="384" y="-160" name="up_down" />
<pin polarity="Output" x="384" y="-96" name="ce" />
<pin polarity="Output" x="384" y="-32" name="error" />
<graph>
<rect width="256" x="64" y="-192" height="192" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin A" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin B" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin up_down" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin ce" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin error" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</graph>
</symbol>

4
toplevel.jhd
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@@ -3,3 +3,7 @@ MODULE toplevel
INSTANCE XLXI_1 INSTANCE XLXI_1
SUBMODULE dds SUBMODULE dds
INSTANCE XLXI_2 INSTANCE XLXI_2
SUBMODULE controller
INSTANCE XLXI_42
SUBMODULE rotary_dec
INSTANCE XLXI_43

306
toplevel.sch
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@@ -6,11 +6,10 @@
<trait edittrait="all:0" /> <trait edittrait="all:0" />
</attr> </attr>
<netlist> <netlist>
<signal name="XLXN_67" />
<signal name="FORM(1:0)" /> <signal name="FORM(1:0)" />
<signal name="FORM(0)"> <signal name="FORM(0)" />
</signal> <signal name="FORM(1)" />
<signal name="FORM(1)">
</signal>
<signal name="CLK_50MHZ" /> <signal name="CLK_50MHZ" />
<signal name="XLXN_9(11:0)" /> <signal name="XLXN_9(11:0)" />
<signal name="XLXN_10" /> <signal name="XLXN_10" />
@@ -18,7 +17,6 @@
<signal name="DAC_CS" /> <signal name="DAC_CS" />
<signal name="SPI_MOSI" /> <signal name="SPI_MOSI" />
<signal name="FREQ(16:0)" /> <signal name="FREQ(16:0)" />
<signal name="FREQ(15:0)" />
<signal name="J18_IO4" /> <signal name="J18_IO4" />
<signal name="J18_IO2" /> <signal name="J18_IO2" />
<signal name="J18_IO3" /> <signal name="J18_IO3" />
@@ -28,8 +26,12 @@
<signal name="LED0" /> <signal name="LED0" />
<signal name="SW0" /> <signal name="SW0" />
<signal name="SW1" /> <signal name="SW1" />
<signal name="XLXN_40" /> <signal name="XLXN_63" />
<signal name="FREQ(16)" /> <signal name="XLXN_64" />
<signal name="XLXN_65" />
<signal name="XLXN_66" />
<signal name="ROT_A" />
<signal name="ROT_B" />
<port polarity="Input" name="CLK_50MHZ" /> <port polarity="Input" name="CLK_50MHZ" />
<port polarity="Output" name="SPI_SCK" /> <port polarity="Output" name="SPI_SCK" />
<port polarity="Output" name="DAC_CS" /> <port polarity="Output" name="DAC_CS" />
@@ -42,6 +44,8 @@
<port polarity="Output" name="LED0" /> <port polarity="Output" name="LED0" />
<port polarity="Input" name="SW0" /> <port polarity="Input" name="SW0" />
<port polarity="Input" name="SW1" /> <port polarity="Input" name="SW1" />
<port polarity="Input" name="ROT_A" />
<port polarity="Input" name="ROT_B" />
<blockdef name="spi_driver"> <blockdef name="spi_driver">
<timestamp>2016-5-20T8:33:2</timestamp> <timestamp>2016-5-20T8:33:2</timestamp>
<rect width="256" x="64" y="-192" height="192" /> <rect width="256" x="64" y="-192" height="192" />
@@ -64,11 +68,6 @@
<rect width="64" x="320" y="-172" height="24" /> <rect width="64" x="320" y="-172" height="24" />
<line x2="384" y1="-160" y2="-160" x1="320" /> <line x2="384" y1="-160" y2="-160" x1="320" />
</blockdef> </blockdef>
<blockdef name="constant">
<timestamp>2006-1-1T10:10:10</timestamp>
<rect width="112" x="0" y="0" height="64" />
<line x2="112" y1="32" y2="32" x1="144" />
</blockdef>
<blockdef name="gnd"> <blockdef name="gnd">
<timestamp>2000-1-1T10:10:10</timestamp> <timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-96" x1="64" /> <line x2="64" y1="-64" y2="-96" x1="64" />
@@ -92,6 +91,33 @@
<line x2="64" y1="0" y2="-32" x1="64" /> <line x2="64" y1="0" y2="-32" x1="64" />
<line x2="32" y1="-64" y2="-64" x1="96" /> <line x2="32" y1="-64" y2="-64" x1="96" />
</blockdef> </blockdef>
<blockdef name="controller">
<timestamp>2016-5-23T16:56:10</timestamp>
<rect width="304" x="64" y="-320" height="320" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<rect width="64" x="368" y="-300" height="24" />
<line x2="432" y1="-288" y2="-288" x1="368" />
</blockdef>
<blockdef name="rotary_dec">
<timestamp>2016-5-23T16:56:27</timestamp>
<rect width="256" x="64" y="-192" height="192" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</blockdef>
<block symbolname="dds" name="XLXI_2">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="FREQ(16:0)" name="freq(16:0)" />
<blockpin signalname="FORM(1:0)" name="form(1:0)" />
<blockpin signalname="XLXN_9(11:0)" name="amp(11:0)" />
</block>
<block symbolname="spi_driver" name="XLXI_1"> <block symbolname="spi_driver" name="XLXI_1">
<blockpin signalname="CLK_50MHZ" name="clk" /> <blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="XLXN_10" name="rst" /> <blockpin signalname="XLXN_10" name="rst" />
@@ -100,26 +126,9 @@
<blockpin signalname="DAC_CS" name="cs" /> <blockpin signalname="DAC_CS" name="cs" />
<blockpin signalname="SPI_MOSI" name="mosi" /> <blockpin signalname="SPI_MOSI" name="mosi" />
</block> </block>
<block symbolname="dds" name="XLXI_2">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="FREQ(16:0)" name="freq(16:0)" />
<blockpin signalname="FORM(1:0)" name="form(1:0)" />
<blockpin signalname="XLXN_9(11:0)" name="amp(11:0)" />
</block>
<block symbolname="gnd" name="XLXI_7"> <block symbolname="gnd" name="XLXI_7">
<blockpin signalname="XLXN_10" name="G" /> <blockpin signalname="XLXN_10" name="G" />
</block> </block>
<block symbolname="gnd" name="XLXI_10">
<blockpin signalname="FREQ(16)" name="G" />
</block>
<block symbolname="constant" name="XLXI_3">
<attr value="03E8" name="CValue">
<trait delete="all:1 sym:0" />
<trait editname="all:1 sch:0" />
<trait valuetype="BitVector 32 Hexadecimal" />
</attr>
<blockpin signalname="FREQ(15:0)" name="O" />
</block>
<block symbolname="buf" name="XLXI_14"> <block symbolname="buf" name="XLXI_14">
<blockpin signalname="SPI_SCK" name="I" /> <blockpin signalname="SPI_SCK" name="I" />
<blockpin signalname="J18_IO4" name="O" /> <blockpin signalname="J18_IO4" name="O" />
@@ -136,13 +145,13 @@
<blockpin signalname="CLK_50MHZ" name="I" /> <blockpin signalname="CLK_50MHZ" name="I" />
<blockpin signalname="J18_IO1" name="O" /> <blockpin signalname="J18_IO1" name="O" />
</block> </block>
<block symbolname="vcc" name="XLXI_20">
<blockpin signalname="XLXN_30" name="P" />
</block>
<block symbolname="buf" name="XLXI_19"> <block symbolname="buf" name="XLXI_19">
<blockpin signalname="XLXN_30" name="I" /> <blockpin signalname="XLXN_30" name="I" />
<blockpin signalname="DAC_CLR" name="O" /> <blockpin signalname="DAC_CLR" name="O" />
</block> </block>
<block symbolname="vcc" name="XLXI_20">
<blockpin signalname="XLXN_30" name="P" />
</block>
<block symbolname="buf" name="XLXI_25"> <block symbolname="buf" name="XLXI_25">
<blockpin signalname="SW0" name="I" /> <blockpin signalname="SW0" name="I" />
<blockpin signalname="FORM(0)" name="O" /> <blockpin signalname="FORM(0)" name="O" />
@@ -155,145 +164,186 @@
<blockpin signalname="SW0" name="I" /> <blockpin signalname="SW0" name="I" />
<blockpin signalname="LED0" name="O" /> <blockpin signalname="LED0" name="O" />
</block> </block>
<block symbolname="controller" name="XLXI_42">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="XLXN_66" name="rst" />
<blockpin signalname="XLXN_65" name="enc_updown" />
<blockpin signalname="XLXN_64" name="enc_ce" />
<blockpin signalname="XLXN_63" name="enc_err" />
<blockpin signalname="FREQ(16:0)" name="freq_out(16:0)" />
</block>
<block symbolname="rotary_dec" name="XLXI_43">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="ROT_A" name="A" />
<blockpin signalname="ROT_B" name="B" />
<blockpin signalname="XLXN_65" name="up_down" />
<blockpin signalname="XLXN_64" name="ce" />
<blockpin signalname="XLXN_63" name="error" />
</block>
<block symbolname="gnd" name="XLXI_44">
<blockpin signalname="XLXN_66" name="G" />
</block>
</netlist> </netlist>
<sheet sheetnum="1" width="3520" height="2720"> <sheet sheetnum="1" width="5440" height="3520">
<instance x="976" y="992" name="XLXI_2" orien="R0"> <instance x="2256" y="1520" name="XLXI_2" orien="R0">
</instance> </instance>
<instance x="1568" y="848" name="XLXI_1" orien="R0"> <instance x="2848" y="1376" name="XLXI_1" orien="R0">
</instance> </instance>
<branch name="FORM(1:0)"> <branch name="FORM(1:0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="848" y="960" type="branch" /> <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2128" y="1488" type="branch" />
<wire x2="848" y1="960" y2="976" x1="848" /> <wire x2="2128" y1="1488" y2="1504" x1="2128" />
<wire x2="848" y1="976" y2="1008" x1="848" /> <wire x2="2128" y1="1504" y2="1536" x1="2128" />
<wire x2="976" y1="960" y2="960" x1="848" /> <wire x2="2256" y1="1488" y2="1488" x1="2128" />
</branch> </branch>
<bustap x2="752" y1="976" y2="976" x1="848" /> <bustap x2="2032" y1="1504" y2="1504" x1="2128" />
<bustap x2="752" y1="1008" y2="1008" x1="848" /> <bustap x2="2032" y1="1536" y2="1536" x1="2128" />
<branch name="FORM(0)"> <branch name="FORM(0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="656" y="976" type="branch" /> <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1936" y="1504" type="branch" />
<wire x2="656" y1="976" y2="976" x1="544" /> <wire x2="1936" y1="1504" y2="1504" x1="1824" />
<wire x2="752" y1="976" y2="976" x1="656" /> <wire x2="2032" y1="1504" y2="1504" x1="1936" />
</branch> </branch>
<branch name="FORM(1)"> <branch name="FORM(1)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="656" y="1040" type="branch" /> <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1936" y="1568" type="branch" />
<wire x2="656" y1="1040" y2="1040" x1="544" /> <wire x2="1936" y1="1568" y2="1568" x1="1824" />
<wire x2="752" y1="1040" y2="1040" x1="656" /> <wire x2="2032" y1="1568" y2="1568" x1="1936" />
<wire x2="752" y1="1008" y2="1040" x1="752" /> <wire x2="2032" y1="1536" y2="1568" x1="2032" />
</branch> </branch>
<branch name="CLK_50MHZ"> <branch name="CLK_50MHZ">
<wire x2="976" y1="832" y2="832" x1="944" /> <wire x2="2256" y1="1360" y2="1360" x1="2224" />
</branch> </branch>
<iomarker fontsize="28" x="944" y="832" name="CLK_50MHZ" orien="R180" />
<branch name="XLXN_9(11:0)"> <branch name="XLXN_9(11:0)">
<wire x2="1456" y1="832" y2="832" x1="1360" /> <wire x2="2736" y1="1360" y2="1360" x1="2640" />
<wire x2="1456" y1="816" y2="832" x1="1456" /> <wire x2="2736" y1="1344" y2="1360" x1="2736" />
<wire x2="1568" y1="816" y2="816" x1="1456" /> <wire x2="2848" y1="1344" y2="1344" x1="2736" />
</branch> </branch>
<instance x="1296" y="736" name="XLXI_7" orien="R0" /> <instance x="2576" y="1264" name="XLXI_7" orien="R0" />
<branch name="XLXN_10"> <branch name="XLXN_10">
<wire x2="1360" y1="544" y2="608" x1="1360" /> <wire x2="2640" y1="1072" y2="1136" x1="2640" />
<wire x2="1440" y1="544" y2="544" x1="1360" /> <wire x2="2720" y1="1072" y2="1072" x1="2640" />
<wire x2="1440" y1="544" y2="752" x1="1440" /> <wire x2="2720" y1="1072" y2="1280" x1="2720" />
<wire x2="1568" y1="752" y2="752" x1="1440" /> <wire x2="2848" y1="1280" y2="1280" x1="2720" />
</branch> </branch>
<branch name="SPI_SCK"> <branch name="SPI_SCK">
<wire x2="1984" y1="688" y2="688" x1="1952" /> <wire x2="3264" y1="1216" y2="1216" x1="3232" />
<wire x2="2112" y1="688" y2="688" x1="1984" /> <wire x2="3392" y1="1216" y2="1216" x1="3264" />
<wire x2="1984" y1="608" y2="688" x1="1984" /> <wire x2="3264" y1="1136" y2="1216" x1="3264" />
<wire x2="2112" y1="608" y2="608" x1="1984" /> <wire x2="3392" y1="1136" y2="1136" x1="3264" />
</branch> </branch>
<branch name="DAC_CS"> <branch name="DAC_CS">
<wire x2="1984" y1="752" y2="752" x1="1952" /> <wire x2="3264" y1="1280" y2="1280" x1="3232" />
<wire x2="2112" y1="752" y2="752" x1="1984" /> <wire x2="3392" y1="1280" y2="1280" x1="3264" />
<wire x2="1984" y1="720" y2="752" x1="1984" /> <wire x2="3264" y1="1248" y2="1280" x1="3264" />
<wire x2="2336" y1="720" y2="720" x1="1984" /> <wire x2="3616" y1="1248" y2="1248" x1="3264" />
</branch> </branch>
<branch name="SPI_MOSI"> <branch name="SPI_MOSI">
<wire x2="1984" y1="816" y2="816" x1="1952" /> <wire x2="3264" y1="1344" y2="1344" x1="3232" />
<wire x2="2112" y1="816" y2="816" x1="1984" /> <wire x2="3392" y1="1344" y2="1344" x1="3264" />
<wire x2="1984" y1="784" y2="816" x1="1984" /> <wire x2="3264" y1="1312" y2="1344" x1="3264" />
<wire x2="2336" y1="784" y2="784" x1="1984" /> <wire x2="3616" y1="1312" y2="1312" x1="3264" />
</branch> </branch>
<branch name="FREQ(16:0)"> <branch name="FREQ(16:0)">
<attrtext style="alignment:SOFT-LEFT;fontsize:28;fontname:Arial" attrname="Name" x="795" y="896" type="branch" /> <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2075" y="1424" type="branch" />
<wire x2="624" y1="816" y2="864" x1="624" /> <wire x2="1904" y1="1152" y2="1152" x1="1664" />
<wire x2="624" y1="864" y2="896" x1="624" /> <wire x2="1904" y1="1152" y2="1344" x1="1904" />
<wire x2="976" y1="896" y2="896" x1="624" /> <wire x2="1904" y1="1344" y2="1424" x1="1904" />
<wire x2="2075" y1="1424" y2="1424" x1="1904" />
<wire x2="2256" y1="1424" y2="1424" x1="2075" />
</branch> </branch>
<bustap x2="528" y1="816" y2="816" x1="624" /> <instance x="3392" y="1168" name="XLXI_14" orien="R0" />
<bustap x2="528" y1="864" y2="864" x1="624" />
<branch name="FREQ(15:0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="464" y="864" type="branch" />
<wire x2="464" y1="864" y2="864" x1="352" />
<wire x2="528" y1="864" y2="864" x1="464" />
</branch>
<instance x="352" y="768" name="XLXI_10" orien="R0" />
<instance x="208" y="832" name="XLXI_3" orien="R0">
</instance>
<instance x="2112" y="640" name="XLXI_14" orien="R0" />
<iomarker fontsize="28" x="2112" y="688" name="SPI_SCK" orien="R0" />
<branch name="J18_IO4"> <branch name="J18_IO4">
<wire x2="2368" y1="608" y2="608" x1="2336" /> <wire x2="3648" y1="1136" y2="1136" x1="3616" />
</branch> </branch>
<iomarker fontsize="28" x="2112" y="752" name="DAC_CS" orien="R0" /> <instance x="3616" y="1280" name="XLXI_15" orien="R0" />
<iomarker fontsize="28" x="2112" y="816" name="SPI_MOSI" orien="R0" /> <instance x="3616" y="1344" name="XLXI_16" orien="R0" />
<instance x="2336" y="752" name="XLXI_15" orien="R0" />
<instance x="2336" y="816" name="XLXI_16" orien="R0" />
<branch name="J18_IO2"> <branch name="J18_IO2">
<wire x2="2592" y1="720" y2="720" x1="2560" /> <wire x2="3872" y1="1248" y2="1248" x1="3840" />
</branch> </branch>
<iomarker fontsize="28" x="2592" y="720" name="J18_IO2" orien="R0" />
<branch name="J18_IO3"> <branch name="J18_IO3">
<wire x2="2592" y1="784" y2="784" x1="2560" /> <wire x2="3872" y1="1312" y2="1312" x1="3840" />
</branch> </branch>
<iomarker fontsize="28" x="2592" y="784" name="J18_IO3" orien="R0" />
<branch name="CLK_50MHZ"> <branch name="CLK_50MHZ">
<wire x2="1552" y1="432" y2="432" x1="1504" /> <wire x2="2832" y1="960" y2="960" x1="2784" />
<wire x2="1552" y1="432" y2="688" x1="1552" /> <wire x2="2832" y1="960" y2="1216" x1="2832" />
<wire x2="1568" y1="688" y2="688" x1="1552" /> <wire x2="2848" y1="1216" y2="1216" x1="2832" />
<wire x2="1664" y1="432" y2="432" x1="1552" /> <wire x2="2944" y1="960" y2="960" x1="2832" />
</branch> </branch>
<instance x="1664" y="464" name="XLXI_17" orien="R0" /> <instance x="2944" y="992" name="XLXI_17" orien="R0" />
<branch name="J18_IO1"> <branch name="J18_IO1">
<wire x2="1920" y1="432" y2="432" x1="1888" /> <wire x2="3200" y1="960" y2="960" x1="3168" />
</branch> </branch>
<iomarker fontsize="28" x="1920" y="432" name="J18_IO1" orien="R0" /> <instance x="3136" y="1840" name="XLXI_19" orien="R0" />
<iomarker fontsize="28" x="2368" y="608" name="J18_IO4" orien="R0" />
<iomarker fontsize="28" x="1504" y="432" name="CLK_50MHZ" orien="R180" />
<instance x="1856" y="1312" name="XLXI_19" orien="R0" />
<branch name="XLXN_30"> <branch name="XLXN_30">
<wire x2="1856" y1="1280" y2="1280" x1="1824" /> <wire x2="3136" y1="1808" y2="1808" x1="3104" />
</branch> </branch>
<branch name="DAC_CLR"> <branch name="DAC_CLR">
<wire x2="2112" y1="1280" y2="1280" x1="2080" /> <wire x2="3392" y1="1808" y2="1808" x1="3360" />
</branch> </branch>
<iomarker fontsize="28" x="2112" y="1280" name="DAC_CLR" orien="R0" /> <instance x="3040" y="1808" name="XLXI_20" orien="R0" />
<instance x="1760" y="1280" name="XLXI_20" orien="R0" />
<branch name="LED0"> <branch name="LED0">
<wire x2="592" y1="1120" y2="1120" x1="544" /> <wire x2="1872" y1="1648" y2="1648" x1="1824" />
</branch> </branch>
<iomarker fontsize="28" x="592" y="1120" name="LED0" orien="R0" /> <instance x="1600" y="1536" name="XLXI_25" orien="R0" />
<instance x="320" y="1008" name="XLXI_25" orien="R0" /> <instance x="1600" y="1600" name="XLXI_26" orien="R0" />
<instance x="320" y="1072" name="XLXI_26" orien="R0" />
<branch name="SW0"> <branch name="SW0">
<wire x2="288" y1="976" y2="976" x1="224" /> <wire x2="1568" y1="1504" y2="1504" x1="1504" />
<wire x2="288" y1="976" y2="1120" x1="288" /> <wire x2="1568" y1="1504" y2="1648" x1="1568" />
<wire x2="320" y1="1120" y2="1120" x1="288" /> <wire x2="1600" y1="1648" y2="1648" x1="1568" />
<wire x2="320" y1="976" y2="976" x1="288" /> <wire x2="1600" y1="1504" y2="1504" x1="1568" />
</branch> </branch>
<branch name="SW1"> <branch name="SW1">
<wire x2="320" y1="1040" y2="1040" x1="224" /> <wire x2="1600" y1="1568" y2="1568" x1="1504" />
</branch> </branch>
<instance x="320" y="1152" name="XLXI_27" orien="R0" /> <instance x="1600" y="1680" name="XLXI_27" orien="R0" />
<iomarker fontsize="28" x="224" y="1040" name="SW1" orien="R180" /> <instance x="1232" y="1440" name="XLXI_42" orien="R0">
<iomarker fontsize="28" x="224" y="976" name="SW0" orien="R180" /> </instance>
<branch name="FREQ(16)"> <instance x="768" y="1440" name="XLXI_43" orien="R0">
<attrtext style="alignment:SOFT-TVCENTER;fontsize:28;fontname:Arial" attrname="Name" x="512" y="736" type="branch" /> </instance>
<wire x2="416" y1="624" y2="640" x1="416" /> <branch name="XLXN_63">
<wire x2="512" y1="624" y2="624" x1="416" /> <wire x2="1232" y1="1408" y2="1408" x1="1152" />
<wire x2="512" y1="624" y2="736" x1="512" />
<wire x2="512" y1="736" y2="816" x1="512" />
<wire x2="528" y1="816" y2="816" x1="512" />
</branch> </branch>
<branch name="XLXN_64">
<wire x2="1232" y1="1344" y2="1344" x1="1152" />
</branch>
<branch name="XLXN_65">
<wire x2="1232" y1="1280" y2="1280" x1="1152" />
</branch>
<instance x="1072" y="1200" name="XLXI_44" orien="R0" />
<branch name="XLXN_66">
<wire x2="1136" y1="1056" y2="1072" x1="1136" />
<wire x2="1184" y1="1056" y2="1056" x1="1136" />
<wire x2="1184" y1="1056" y2="1216" x1="1184" />
<wire x2="1232" y1="1216" y2="1216" x1="1184" />
</branch>
<branch name="CLK_50MHZ">
<wire x2="1216" y1="976" y2="976" x1="1136" />
<wire x2="1216" y1="976" y2="1152" x1="1216" />
<wire x2="1232" y1="1152" y2="1152" x1="1216" />
</branch>
<branch name="ROT_A">
<wire x2="768" y1="1344" y2="1344" x1="736" />
</branch>
<branch name="ROT_B">
<wire x2="768" y1="1408" y2="1408" x1="736" />
</branch>
<branch name="CLK_50MHZ">
<wire x2="768" y1="1280" y2="1280" x1="736" />
</branch>
<iomarker fontsize="28" x="2224" y="1360" name="CLK_50MHZ" orien="R180" />
<iomarker fontsize="28" x="3392" y="1216" name="SPI_SCK" orien="R0" />
<iomarker fontsize="28" x="3392" y="1280" name="DAC_CS" orien="R0" />
<iomarker fontsize="28" x="3392" y="1344" name="SPI_MOSI" orien="R0" />
<iomarker fontsize="28" x="3872" y="1248" name="J18_IO2" orien="R0" />
<iomarker fontsize="28" x="3872" y="1312" name="J18_IO3" orien="R0" />
<iomarker fontsize="28" x="3200" y="960" name="J18_IO1" orien="R0" />
<iomarker fontsize="28" x="3648" y="1136" name="J18_IO4" orien="R0" />
<iomarker fontsize="28" x="2784" y="960" name="CLK_50MHZ" orien="R180" />
<iomarker fontsize="28" x="3392" y="1808" name="DAC_CLR" orien="R0" />
<iomarker fontsize="28" x="1872" y="1648" name="LED0" orien="R0" />
<iomarker fontsize="28" x="1504" y="1568" name="SW1" orien="R180" />
<iomarker fontsize="28" x="1504" y="1504" name="SW0" orien="R180" />
<iomarker fontsize="28" x="1136" y="976" name="CLK_50MHZ" orien="R180" />
<iomarker fontsize="28" x="736" y="1344" name="ROT_A" orien="R180" />
<iomarker fontsize="28" x="736" y="1408" name="ROT_B" orien="R180" />
<iomarker fontsize="28" x="736" y="1280" name="CLK_50MHZ" orien="R180" />
</sheet> </sheet>
</drawing> </drawing>

33
yasg.gise
View File

@@ -30,6 +30,11 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="controller.prj"/>
<file xil_pn:fileType="FILE_SPL" xil_pn:name="controller.spl"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="controller.stx"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="controller.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="controller.xst"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="dds.bld"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="dds.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="dds.cmd_log"/> <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="dds.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="dds.lso"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="dds.lso"/>
@@ -69,6 +74,11 @@
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/> <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/> <file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="rotary_dec.prj"/>
<file xil_pn:fileType="FILE_SPL" xil_pn:name="rotary_dec.spl"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="rotary_dec.stx"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="rotary_dec.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="rotary_dec.xst"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="spi_driver.cmd_log"/> <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="spi_driver.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="spi_driver.lso"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="spi_driver.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="spi_driver.ngc"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="spi_driver.ngc"/>
@@ -144,6 +154,7 @@
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="dds.vhd"/> <outfile xil_pn:name="dds.vhd"/>
@@ -215,7 +226,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463744693" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1463744692"> <transform xil_pn:end_ts="1464023169" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1464023167">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="toplevel.vhf"/> <outfile xil_pn:name="toplevel.vhf"/>
@@ -240,7 +251,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463744766" xil_pn:in_ck="-1719981268874910048" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1463744693"> <transform xil_pn:end_ts="1464023279" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1464023169">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
@@ -261,11 +272,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1463744766" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1463744766"> <transform xil_pn:end_ts="1464023279" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1464023279">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463744772" xil_pn:in_ck="2169537708537049843" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1463744766"> <transform xil_pn:end_ts="1464023287" xil_pn:in_ck="2169537708537049843" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1464023279">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
@@ -274,7 +285,7 @@
<outfile xil_pn:name="toplevel.ngd"/> <outfile xil_pn:name="toplevel.ngd"/>
<outfile xil_pn:name="toplevel_ngdbuild.xrpt"/> <outfile xil_pn:name="toplevel_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1463744783" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1463744772"> <transform xil_pn:end_ts="1464023306" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1464023287">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
@@ -290,8 +301,9 @@
<outfile xil_pn:name="toplevel_summary.xml"/> <outfile xil_pn:name="toplevel_summary.xml"/>
<outfile xil_pn:name="toplevel_usage.xml"/> <outfile xil_pn:name="toplevel_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1463744826" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1463744783"> <transform xil_pn:end_ts="1464023444" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1464023306">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="toplevel.ncd"/> <outfile xil_pn:name="toplevel.ncd"/>
@@ -304,7 +316,7 @@
<outfile xil_pn:name="toplevel_pad.txt"/> <outfile xil_pn:name="toplevel_pad.txt"/>
<outfile xil_pn:name="toplevel_par.xrpt"/> <outfile xil_pn:name="toplevel_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1463744842" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1463744826"> <transform xil_pn:end_ts="1464023466" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1464023444">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -316,13 +328,12 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1463743826" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1463743825"> <transform xil_pn:end_ts="1464023484" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1464023483">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform> </transform>
<transform xil_pn:end_ts="1463744826" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1463744821"> <transform xil_pn:end_ts="1464023444" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1464023434">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

12
yasg.xise
View File

@@ -21,7 +21,7 @@
</file> </file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -45,11 +45,19 @@
</file> </file>
<file xil_pn:name="toplevel.sch" xil_pn:type="FILE_SCHEMATIC"> <file xil_pn:name="toplevel.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="io.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="io.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="rotary.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
</files> </files>
<properties> <properties>