From bc78a4070832a1964b79579fa7eb2a7ba53f710e Mon Sep 17 00:00:00 2001 From: T-moe Date: Mon, 23 May 2016 19:22:33 +0200 Subject: [PATCH] Added rotary decoder and simple controller --- controller.sym | 28 +++++ controller.vhd | 70 +++++++++++ dds.vhd | 2 +- io.ucf | 5 +- rotary.vhd | 65 +++++++++++ rotary_dec.sym | 27 +++++ toplevel.jhd | 4 + toplevel.sch | 306 ++++++++++++++++++++++++++++--------------------- yasg.gise | 33 ++++-- yasg.xise | 12 +- 10 files changed, 409 insertions(+), 143 deletions(-) create mode 100644 controller.sym create mode 100644 controller.vhd create mode 100644 rotary.vhd create mode 100644 rotary_dec.sym diff --git a/controller.sym b/controller.sym new file mode 100644 index 0000000..edf28fc --- /dev/null +++ b/controller.sym @@ -0,0 +1,28 @@ + + + BLOCK + 2016-5-23T16:56:10 + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/controller.vhd b/controller.vhd new file mode 100644 index 0000000..437f611 --- /dev/null +++ b/controller.vhd @@ -0,0 +1,70 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 18:47:36 05/23/2016 +-- Design Name: +-- Module Name: controller - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity controller is + Port ( clk : in STD_LOGIC; + rst: in STD_LOGIC; + enc_updown : in STD_LOGIC; + enc_ce : in STD_LOGIC; + enc_err : in STD_LOGIC; + freq_out : out unsigned (16 downto 0)); +end controller; + +architecture Behavioral of controller is + signal freq_reg, freq_next : unsigned(16 downto 0) := to_unsigned(1000,17); +begin + + proc1: process(clk,rst) + begin + if(rst='1') then + freq_reg <= to_unsigned(1000,17); + elsif(rising_edge(clk)) then + freq_reg <= freq_next; + end if; + end process proc1; + + freq_out <= freq_reg; + + proc2: process(freq_reg,enc_updown,enc_ce,enc_err) + begin + freq_next <= freq_reg; + if(enc_ce='1' and enc_err='0') then + if(enc_updown='1') then + freq_next <= freq_reg + 1; + else + freq_next <= freq_reg - 1; + end if; + end if; + + end process proc2; + +end Behavioral; + diff --git a/dds.vhd b/dds.vhd index ec2b843..95b8798 100644 --- a/dds.vhd +++ b/dds.vhd @@ -55,7 +55,7 @@ begin -- m = fout*(2^n)/fclk m <= resize(divide(shift_left(resize(freq,64),acc_res),to_unsigned(clk_freq,64)),m'length); - idx_phase <= idx(acc_res -1 downto acc_res - phase_res); + idx_phase <= idx(acc_res -1 downto acc_res - phase_res); amp_rect <= to_unsigned(0,adc_res) when idx_phase(phase_res-1)='0' else to_unsigned((2**adc_res)-1,adc_res); diff --git a/io.ucf b/io.ucf index 5865944..24d0206 100644 --- a/io.ucf +++ b/io.ucf @@ -16,4 +16,7 @@ NET "J18_IO4" LOC = "AB19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 NET "LED0" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "SW0" LOC = "V8" | IOSTANDARD = LVCMOS33 ; -NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ; \ No newline at end of file +NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ; + +NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP; +NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP; \ No newline at end of file diff --git a/rotary.vhd b/rotary.vhd new file mode 100644 index 0000000..ca11399 --- /dev/null +++ b/rotary.vhd @@ -0,0 +1,65 @@ +----------------------------------------------------------------------------- +-- +-- Decoder für Drehgeber +-- +----------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rotary_dec is + Port ( clk : in std_logic; -- Systemtakt + A : in std_logic; -- Spur A + B : in std_logic; -- Spur B + up_down : out std_logic; -- Zaehlrichtung + ce : out std_logic; -- Clock Enable + error : out std_logic); -- illegaler Signalübergang +end rotary_dec; + +architecture Behavioral of rotary_dec is + +signal a_in, b_in, a_old, b_old: std_logic; + +begin + +-- Abtastung und Verzoegerung der Quadratursignale + +process(clk) +begin + if rising_edge(clk) then + a_old <= a_in; + a_in <= A; + b_old <= b_in; + b_in <= B; + end if; +end process; + +-- Dekodierung der Ausgaenge + +process(a_in, b_in, a_old, b_old) +variable state: std_logic_vector(3 downto 0); +begin + state := a_in & b_in & a_old & b_old; + case state is + when "0000" => up_down <= '0'; ce <= '0'; error <= '0'; + when "0001" => up_down <= '1'; ce <= '1'; error <= '0'; + when "0010" => up_down <= '0'; ce <= '1'; error <= '0'; + when "0011" => up_down <= '0'; ce <= '0'; error <= '1'; + when "0100" => up_down <= '0'; ce <= '1'; error <= '0'; + when "0101" => up_down <= '0'; ce <= '0'; error <= '0'; + when "0110" => up_down <= '0'; ce <= '0'; error <= '1'; + when "0111" => up_down <= '1'; ce <= '1'; error <= '0'; + when "1000" => up_down <= '1'; ce <= '1'; error <= '0'; + when "1001" => up_down <= '0'; ce <= '0'; error <= '1'; + when "1010" => up_down <= '0'; ce <= '0'; error <= '0'; + when "1011" => up_down <= '0'; ce <= '1'; error <= '0'; + when "1100" => up_down <= '0'; ce <= '0'; error <= '1'; + when "1101" => up_down <= '0'; ce <= '1'; error <= '0'; + when "1110" => up_down <= '1'; ce <= '1'; error <= '0'; + when "1111" => up_down <= '0'; ce <= '0'; error <= '0'; + when others => null; + end case; +end process; + +end Behavioral; + diff --git a/rotary_dec.sym b/rotary_dec.sym new file mode 100644 index 0000000..f48b8dc --- /dev/null +++ b/rotary_dec.sym @@ -0,0 +1,27 @@ + + + BLOCK + 2016-5-23T16:56:27 + + + + + + + + + + + + + + + + + + + + + + + diff --git a/toplevel.jhd b/toplevel.jhd index 5880a97..d1c361a 100644 --- a/toplevel.jhd +++ b/toplevel.jhd @@ -3,3 +3,7 @@ MODULE toplevel INSTANCE XLXI_1 SUBMODULE dds INSTANCE XLXI_2 + SUBMODULE controller + INSTANCE XLXI_42 + SUBMODULE rotary_dec + INSTANCE XLXI_43 diff --git a/toplevel.sch b/toplevel.sch index cdb795b..c2f21e0 100644 --- a/toplevel.sch +++ b/toplevel.sch @@ -6,11 +6,10 @@ + - - - - + + @@ -18,7 +17,6 @@ - @@ -28,8 +26,12 @@ - - + + + + + + @@ -42,6 +44,8 @@ + + 2016-5-20T8:33:2 @@ -64,11 +68,6 @@ - - 2006-1-1T10:10:10 - - - 2000-1-1T10:10:10 @@ -92,6 +91,33 @@ + + 2016-5-23T16:56:10 + + + + + + + + + + + 2016-5-23T16:56:27 + + + + + + + + + + + + + + @@ -100,26 +126,9 @@ - - - - - - - - - - - - - - - - - @@ -136,13 +145,13 @@ - - - + + + @@ -155,145 +164,186 @@ + + + + + + + + + + + + + + + + + + + - - + + - + - - - - + + + + - - + + - - - + + + - - - - + + + + - + - - - - + + + - + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + + + - - - - - - - - - - - - + - + - - - - + + - + - - + - - - - - + + + + - + - + - - - - + - + - + - - + - + - - - + + - - - - + + + + - + - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/yasg.gise b/yasg.gise index 64b62a6..51e396f 100644 --- a/yasg.gise +++ b/yasg.gise @@ -30,6 +30,11 @@ + + + + + @@ -69,6 +74,11 @@ + + + + + @@ -144,6 +154,7 @@ + @@ -215,7 +226,7 @@ - + @@ -240,7 +251,7 @@ - + @@ -261,11 +272,11 @@ - + - + @@ -274,7 +285,7 @@ - + @@ -290,8 +301,9 @@ - + + @@ -304,7 +316,7 @@ - + @@ -316,13 +328,12 @@ - + + - - - + diff --git a/yasg.xise b/yasg.xise index d2d0d17..b50633d 100644 --- a/yasg.xise +++ b/yasg.xise @@ -21,7 +21,7 @@ - + @@ -45,11 +45,19 @@ - + + + + + + + + +