Added SPI driver.

spi_driver.vhd

@@ -0,0 +1,85 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    12:51:31 05/17/2016 
+-- Design Name: 
+-- Module Name:    spi_driver - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity spi_driver is
+	Generic (clk_freq: natural:= 50000000;
+             adc_res: natural:=12);
+    Port ( clk : in  STD_LOGIC;
+			  rst: in STD_LOGIC;
+           val : in  unsigned (adc_res-1 downto 0);
+           sck : out  STD_LOGIC;
+           cs : out  STD_LOGIC;
+           mosi : out  STD_LOGIC);
+end spi_driver;
+
+architecture Behavioral of spi_driver is
+	type states is(S_IDLE, S_WORK);
+	signal state_reg, state_next: states := S_IDLE;
+	signal counter, counter_next: unsigned(5 downto 0) := (others => '0'); 
+	signal data: unsigned(23 downto 0);
+begin
+	REGS: process (clk, rst) is
+	begin                                   -- process start
+	  if rst = '1' then                 -- asynchronous reset (active high)
+			state_reg <= S_IDLE;
+			counter <= to_unsigned(0,counter'length);
+	  elsif rising_edge(clk) then         -- rising clock edge
+			state_reg <= state_next;
+			counter <= counter_next;
+	  end if;
+	end process REGS;
+
+	data(23 downto 20) <= "0011";  --Command: Write to and Update (Power Up) 
+	data(19 downto 16) <= "0000";  --Adress: DAC0
+	data(15 downto 4) <= val; -- DAC Value (12bit)
+	data(3 downto 0) <= "0000"; -- 4x don't care
+
+	mosi <= data(23 - to_integer(counter srl 1)) when state_reg=S_WORK else '0';
+	sck <= '1' when state_reg=S_WORK and counter(0)='1' else '0';
+	cs <= '1' when state_reg =S_IDLE else '0';
+
+	NSL: process (state_reg, counter) is
+	begin   
+		state_next <= state_reg;
+		counter_next <= counter;
+		case state_reg is -- switch on current state
+			when S_IDLE => -- currently in idle state
+				state_next <= S_WORK;
+				counter_next <= to_unsigned(0,counter'length);
+			when S_WORK => -- currently in work state
+				if(counter = 24*2 -1) then
+					state_next <= S_IDLE;
+				else
+					counter_next<= counter + 1;
+				end if;
+			when others => null; -- do nothing, if we are in a different state
+		end case;	
+	end process NSL;
+
+end Behavioral;
+

spi_driver_tb.vhd

@@ -0,0 +1,118 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   15:38:41 05/17/2016
+-- Design Name:   
+-- Module Name:   /home/timo/vhdl-yasg/spi_driver_tb.vhd
+-- Project Name:  yasg
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: spi_driver
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+ 
+ENTITY spi_driver_tb IS
+END spi_driver_tb;
+ 
+ARCHITECTURE behavior OF spi_driver_tb IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT spi_driver
+    PORT(
+         clk : IN  std_logic;
+         rst : IN  std_logic;
+         val : IN  unsigned(11 downto 0);
+         sck : OUT  std_logic;
+         cs : OUT  std_logic;
+         mosi : OUT  std_logic
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk : std_logic := '0';
+   signal rst : std_logic := '0';
+   signal val : unsigned(11 downto 0) := (others => '0');
+
+ 	--Outputs
+   signal sck : std_logic;
+   signal cs : std_logic;
+   signal mosi : std_logic;
+
+   -- Clock period definitions
+   constant clk_period : time := 20 ns; --50mhz
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: spi_driver PORT MAP (
+          clk => clk,
+          rst => rst,
+          val => val,
+          sck => sck,
+          cs => cs,
+          mosi => mosi
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+		clk <= '0';
+		wait for clk_period/2;
+		clk <= '1';
+		wait for clk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state for 100 ns.
+		rst <= '1';
+      wait for 100 ns;	
+		rst <= '0';
+      wait for clk_period*10;
+		
+		val <= to_unsigned(0,12);
+		wait for clk_period*64;
+		
+		val <= to_unsigned(7,12);
+		wait for clk_period*64;
+		
+		val <= to_unsigned(31,12);
+		wait for clk_period*64;
+		
+		val <= to_unsigned(128,12);
+		wait for clk_period*64;
+		
+		val <= to_unsigned(512,12);
+		wait for clk_period*64;
+
+      -- insert stimulus here 
+
+      wait;
+   end process;
+
+END;

yasg.gise

@@ -37,19 +37,30 @@
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="dds.xst"/>
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_envsettings.html"/>
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_summary.html"/>
-    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="dds_tb_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="dds_tb_isim_beh.wdb"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_stx_beh.prj"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_vhdl.prj"/>
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="dds_xst.xrpt"/>
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
-    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
     <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/>
     <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/>
     <file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/>
+    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="spi_driver.cmd_log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="spi_driver.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="spi_driver.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="spi_driver.ngr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_driver.prj"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="spi_driver.stx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="spi_driver.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="spi_driver.xst"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_envsettings.html"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_summary.html"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_driver_tb_beh.prj"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_tb_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="spi_driver_tb_isim_beh.wdb"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_driver_xst.xrpt"/>
     <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
@@ -60,100 +71,101 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463480524" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463480524">
+    <transform xil_pn:end_ts="1463492912" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463492912">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="dds.vhd"/>
       <outfile xil_pn:name="dds_tb.vhd"/>
       <outfile xil_pn:name="helpers.vhd"/>
       <outfile xil_pn:name="lcd_driver.vhd"/>
+      <outfile xil_pn:name="spi_driver.vhd"/>
+      <outfile xil_pn:name="spi_driver_tb.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1463390593" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8944967924106743327" xil_pn:start_ts="1463390593">
+    <transform xil_pn:end_ts="1463492818" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="9076618275249177275" xil_pn:start_ts="1463492818">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463390593" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5140074775533282471" xil_pn:start_ts="1463390593">
+    <transform xil_pn:end_ts="1463492818" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="983764721944091843" xil_pn:start_ts="1463492818">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463391355" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-5493774896299751744" xil_pn:start_ts="1463391355">
+    <transform xil_pn:end_ts="1463492319" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="7922287241511046268" xil_pn:start_ts="1463492319">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463480524" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463480524">
+    <transform xil_pn:end_ts="1463492912" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463492912">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="dds.vhd"/>
       <outfile xil_pn:name="dds_tb.vhd"/>
       <outfile xil_pn:name="helpers.vhd"/>
       <outfile xil_pn:name="lcd_driver.vhd"/>
+      <outfile xil_pn:name="spi_driver.vhd"/>
+      <outfile xil_pn:name="spi_driver_tb.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1463480530" xil_pn:in_ck="-1527320413769792740" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6917596232395121981" xil_pn:start_ts="1463480524">
+    <transform xil_pn:end_ts="1463492916" xil_pn:in_ck="-5764019863604259361" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6914626614812979269" xil_pn:start_ts="1463492912">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="dds_tb_beh.prj"/>
-      <outfile xil_pn:name="dds_tb_isim_beh.exe"/>
       <outfile xil_pn:name="fuse.log"/>
       <outfile xil_pn:name="isim"/>
-      <outfile xil_pn:name="isim.log"/>
+      <outfile xil_pn:name="spi_driver_tb_beh.prj"/>
+      <outfile xil_pn:name="spi_driver_tb_isim_beh.exe"/>
       <outfile xil_pn:name="xilinxsim.ini"/>
     </transform>
-    <transform xil_pn:end_ts="1463480530" xil_pn:in_ck="5986968781955972703" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1463480530">
+    <transform xil_pn:end_ts="1463492916" xil_pn:in_ck="3473449341593533562" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4788567445176171336" xil_pn:start_ts="1463492916">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="dds_tb_isim_beh.wdb"/>
       <outfile xil_pn:name="isim.cmd"/>
-      <outfile xil_pn:name="isim.log"/>
+      <outfile xil_pn:name="spi_driver_tb_isim_beh.wdb"/>
     </transform>
     <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1463390963">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4734209280692859583" xil_pn:start_ts="1463390963">
+    <transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4283474513315137243" xil_pn:start_ts="1463492899">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5493774896299751744" xil_pn:start_ts="1463390963">
+    <transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7922287241511046268" xil_pn:start_ts="1463492899">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1463390963">
+    <transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1463492899">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6025362818043660137" xil_pn:start_ts="1463390963">
+    <transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6021373413463586381" xil_pn:start_ts="1463492899">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1463390963">
+    <transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1463492899">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463390963" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6649507734898087542" xil_pn:start_ts="1463390963">
+    <transform xil_pn:end_ts="1463492899" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5717942653304215546" xil_pn:start_ts="1463492899">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1463480235" xil_pn:in_ck="-8475077075915550756" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7698400163542717516" xil_pn:start_ts="1463480154">
+    <transform xil_pn:end_ts="1463492907" xil_pn:in_ck="-2379736742458753213" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="3948038486698552048" xil_pn:start_ts="1463492899">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name=".lso"/>
       <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
-      <outfile xil_pn:name="dds.lso"/>
+      <outfile xil_pn:name="spi_driver.lso"/>
-      <outfile xil_pn:name="dds.ngc"/>
+      <outfile xil_pn:name="spi_driver.ngc"/>
-      <outfile xil_pn:name="dds.ngr"/>
+      <outfile xil_pn:name="spi_driver.ngr"/>
-      <outfile xil_pn:name="dds.prj"/>
+      <outfile xil_pn:name="spi_driver.prj"/>
-      <outfile xil_pn:name="dds.stx"/>
+      <outfile xil_pn:name="spi_driver.stx"/>
-      <outfile xil_pn:name="dds.syr"/>
+      <outfile xil_pn:name="spi_driver.syr"/>
-      <outfile xil_pn:name="dds.xst"/>
+      <outfile xil_pn:name="spi_driver.xst"/>
-      <outfile xil_pn:name="dds_tb_beh.prj"/>
+      <outfile xil_pn:name="spi_driver_tb_beh.prj"/>
-      <outfile xil_pn:name="dds_tb_stx_beh.prj"/>
+      <outfile xil_pn:name="spi_driver_xst.xrpt"/>
-      <outfile xil_pn:name="dds_xst.xrpt"/>
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>

yasg.xise

@@ -20,19 +20,29 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
     </file>
+    <file xil_pn:name="spi_driver.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="spi_driver_tb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="48"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/>
+    </file>
   </files>
 
   <properties>
@@ -40,23 +50,24 @@
     <property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3AN Starter Kit" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|dds|Behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spi_driver|Behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="dds.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="spi_driver.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/dds" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spi_driver" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/dds_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spi_driver_tb" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.dds_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spi_driver_tb" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|dds_tb|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|spi_driver_tb|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>