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Merge remote-tracking branch 'origin/feature/dds'

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id101010
2016-06-03 16:27:55 +02:00
parent 4c0ab1b7b4 ecdaaccee5
commit 6769253ef3
20 changed files with 1418 additions and 141 deletions
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1
.gitignore vendored
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!*.wcfg !*.wcfg
!*/ !*/
!documentation/* !documentation/*
!screenshots/*

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controller.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="controller">
<symboltype>BLOCK</symboltype>
<timestamp>2016-6-3T12:59:50</timestamp>
<pin polarity="Input" x="0" y="-352" name="clk" />
<pin polarity="Input" x="0" y="-288" name="rst" />
<pin polarity="Input" x="0" y="-32" name="enc_err" />
<pin polarity="Output" x="432" y="-352" name="freq_out(16:0)" />
<pin polarity="Input" x="0" y="-224" name="enc_btn" />
<pin polarity="Input" x="0" y="-96" name="enc_ce" />
<pin polarity="Input" x="0" y="-160" name="enc_updown" />
<graph>
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="216" y="-392" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin clk" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin rst" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin enc_err" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-352" type="pin freq_out(16:0)" />
<rect width="64" x="368" y="-364" height="24" />
<line x2="432" y1="-352" y2="-352" x1="368" />
<rect width="304" x="64" y="-384" height="384" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="76" y="-224" type="pin enc_btn" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin enc_ce" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin enc_updown" />
</graph>
</symbol>

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controller.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:47:36 05/23/2016
-- Design Name:
-- Module Name: controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity controller is
Port ( clk : in STD_LOGIC;
rst: in STD_LOGIC;
enc_updown : in STD_LOGIC;
enc_ce : in STD_LOGIC;
enc_btn: in STD_LOGIC;
enc_err : in STD_LOGIC;
freq_out : out unsigned (16 downto 0));
end controller;
architecture Behavioral of controller is
signal freq_reg, freq_next : unsigned(16 downto 0) := to_unsigned(1000,17);
signal digpos_reg, digpos_next : unsigned(2 downto 0) := to_unsigned(0,3);
signal btn_old_reg, btn_old_next : std_logic := '0';
type storage is array (4 downto 0) of unsigned (16 downto 0);
constant bases : storage := (to_unsigned(1,17),to_unsigned(10,17),
to_unsigned(100,17),to_unsigned(1000,17),
to_unsigned(10000,17));
signal digpos_base : unsigned(16 downto 0);
begin
proc1: process(clk,rst)
begin
if(rst='1') then
freq_reg <= to_unsigned(1000,17);
digpos_reg <= to_unsigned(0,3);
btn_old_reg <= '0';
elsif(rising_edge(clk)) then
freq_reg <= freq_next;
digpos_reg <= digpos_next;
btn_old_reg <= btn_old_next;
end if;
end process proc1;
freq_out <= freq_reg;
digpos_base <= bases(to_integer(digpos_reg));
proc2: process(freq_reg,enc_updown,enc_ce,enc_err,enc_btn,digpos_reg,digpos_base,btn_old_reg)
begin
freq_next <= freq_reg;
digpos_next <= digpos_reg;
btn_old_next <= enc_btn;
if(enc_ce='1' and enc_err='0') then
if(enc_updown='1') then
freq_next <= freq_reg + digpos_base;
else
freq_next <= freq_reg - digpos_base;
end if;
elsif(enc_btn ='1' and btn_old_reg='0') then
if(digpos_reg = to_unsigned(4,3)) then
digpos_next <= to_unsigned(0,3);
else
digpos_next <= digpos_reg + 1;
end if;
end if;
end process proc2;
end Behavioral;

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dds.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="dds">
<symboltype>BLOCK</symboltype>
<timestamp>2016-5-20T8:58:58</timestamp>
<pin polarity="Input" x="0" y="-160" name="clk" />
<pin polarity="Input" x="0" y="-96" name="freq(16:0)" />
<pin polarity="Input" x="0" y="-32" name="form(1:0)" />
<pin polarity="Output" x="384" y="-160" name="amp(11:0)" />
<graph>
<rect width="256" x="64" y="-192" height="192" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin freq(16:0)" />
<rect width="64" x="0" y="-108" height="24" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin form(1:0)" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin amp(11:0)" />
<rect width="64" x="320" y="-172" height="24" />
<line x2="384" y1="-160" y2="-160" x1="320" />
</graph>
</symbol>

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dds.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:09:53 05/16/2016
-- Design Name:
-- Module Name: dds - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use work.helpers.all;
entity dds is
Generic (clk_freq: natural:= 50000000;
freq_res: natural:=17; -- width of frequency input (log2(max_freq))
adc_res: natural:=12; -- width of the ouput signal (=adc resolution)
acc_res: natural:=32; -- width of the phase accumulator
phase_res: natural:=10); -- effective phase resolution for sin lookup table
Port ( clk : in STD_LOGIC;
freq : in unsigned (freq_res-1 downto 0);
form : in unsigned (1 downto 0);
amp : out unsigned (adc_res-1 downto 0));
end dds;
architecture Behavioral of dds is
signal m, idx : unsigned(acc_res -1 downto 0):= (others => '0');
signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0');
signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0);
type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0);
--type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
function gen_sin_wave return storage is
variable temp : storage;
begin
forLoop: for i in 0 to temp'high loop
temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1);
--temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1) + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);
end loop;
return temp;
end function gen_sin_wave;
constant sin_wave : storage := gen_sin_wave;
begin
-- m = fout*(2^n)/fclk = fout*((2^n)*(2^k)/fclk)/(2^k) with k=ceil(log2(fclk)), n=acc_res
m <= resize( (resize(freq,64)
*
(shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq))
/to_unsigned(2**log2_int(clk_freq),64),acc_res);
amp_rect <= to_unsigned(0,adc_res) when idx(acc_res-1)='0' else
to_unsigned((2**adc_res)-1,adc_res);
amp_saw <= idx(acc_res -1 downto acc_res - adc_res);
amp_tria <= idx(acc_res -2 downto acc_res - adc_res) & "0"
when idx(acc_res-1)='0' else
((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res) & "0");
idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
--amp_sin <= sin_wave(to_integer(idx_phase));
amp_sin <= to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="01" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="10" else
to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0)));
with form select amp <= amp_rect when "00",
amp_saw when "01",
amp_tria when "10",
amp_sin when others;
P1: process(clk)
begin
if(rising_edge(clk)) then
idx <= (idx+m);
end if;
end process P1;
end Behavioral;

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dds_tb.vhd Normal file
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:35:57 05/16/2016
-- Design Name:
-- Module Name: /home/timo/vhdl-yasg/dds_tb.vhd
-- Project Name: yasg
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: dds
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY dds_tb IS
END dds_tb;
ARCHITECTURE behavior OF dds_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dds
PORT(
clk : IN std_logic;
freq : IN unsigned(16 downto 0);
form : IN unsigned(1 downto 0);
amp : OUT unsigned(11 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal freq : unsigned(16 downto 0) := (others => '0');
signal form : unsigned(1 downto 0) := (others => '0');
--Outputs
signal amp : unsigned(11 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns; --50mhz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dds PORT MAP (
clk => clk,
freq => freq,
form => form,
amp => amp
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
form <= "00";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
form <= "01";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
form <= "10";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
form <= "11";
freq <= to_unsigned(50000,17);
wait for 40 us;
freq <= to_unsigned(100000,17);
wait for 20 us;
wait;
end process;
END;

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helpers.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package helpers is
--helper function to calculate the log2 (truncated) of a integer
function log2_int(n:natural) return natural;
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
end helpers;
package body helpers is
function log2_int(n:natural) return natural is
begin
if(n>1) then --we can stil divide n by 2
return 1+log2_int(n/2); --recursivly call log2_int for the by two divided number.
end if;
return 1; --since we can no longer divide n, return 1
end log2_int;
--Source: http://vhdlguru.blogspot.ch/2010/03/vhdl-function-for-division-two-signed.html
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
variable a1 : unsigned(a'length-1 downto 0):=a;
variable b1 : unsigned(b'length-1 downto 0):=b;
variable p1 : unsigned(b'length downto 0):= (others => '0');
variable i : integer:=0;
begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;
end helpers;

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io.ucf Normal file
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NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
NET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CS" LOC = "W7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CLR" LOC = "AB13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "DAC_OUT" LOC = "V7" | IOSTANDARD = LVCMOS33
NET "J18_IO1" LOC = "AA21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "J18_IO2" LOC = "AB21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "J18_IO3" LOC = "AA19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "J18_IO4" LOC = "AB19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "LED0" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SW0" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ;
NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN;

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rotary.vhd Normal file
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-----------------------------------------------------------------------------
--
-- Decoder für Drehgeber
--
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rotary_dec is
Port ( clk : in std_logic; -- Systemtakt
A : in std_logic; -- Spur A
B : in std_logic; -- Spur B
up_down : out std_logic; -- Zaehlrichtung
ce : out std_logic; -- Clock Enable
error : out std_logic); -- illegaler Signalübergang
end rotary_dec;
architecture Behavioral of rotary_dec is
signal a_in, b_in, a_old, b_old: std_logic;
begin
-- Abtastung und Verzoegerung der Quadratursignale
process(clk)
begin
if rising_edge(clk) then
a_old <= a_in;
a_in <= A;
b_old <= b_in;
b_in <= B;
end if;
end process;
-- Dekodierung der Ausgaenge
process(a_in, b_in, a_old, b_old)
variable state: std_logic_vector(3 downto 0);
begin
state := a_in & b_in & a_old & b_old;
case state is
when "0000" => up_down <= '0'; ce <= '0'; error <= '0';
when "0001" => up_down <= '1'; ce <= '1'; error <= '0';
when "0010" => up_down <= '0'; ce <= '1'; error <= '0';
when "0011" => up_down <= '0'; ce <= '0'; error <= '1';
when "0100" => up_down <= '0'; ce <= '1'; error <= '0';
when "0101" => up_down <= '0'; ce <= '0'; error <= '0';
when "0110" => up_down <= '0'; ce <= '0'; error <= '1';
when "0111" => up_down <= '1'; ce <= '1'; error <= '0';
when "1000" => up_down <= '1'; ce <= '1'; error <= '0';
when "1001" => up_down <= '0'; ce <= '0'; error <= '1';
when "1010" => up_down <= '0'; ce <= '0'; error <= '0';
when "1011" => up_down <= '0'; ce <= '1'; error <= '0';
when "1100" => up_down <= '0'; ce <= '0'; error <= '1';
when "1101" => up_down <= '0'; ce <= '1'; error <= '0';
when "1110" => up_down <= '1'; ce <= '1'; error <= '0';
when "1111" => up_down <= '0'; ce <= '0'; error <= '0';
when others => null;
end case;
end process;
end Behavioral;

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rotary_dec.sym Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="rotary_dec">
<symboltype>BLOCK</symboltype>
<timestamp>2016-5-23T16:56:27</timestamp>
<pin polarity="Input" x="0" y="-160" name="clk" />
<pin polarity="Input" x="0" y="-96" name="A" />
<pin polarity="Input" x="0" y="-32" name="B" />
<pin polarity="Output" x="384" y="-160" name="up_down" />
<pin polarity="Output" x="384" y="-96" name="ce" />
<pin polarity="Output" x="384" y="-32" name="error" />
<graph>
<rect width="256" x="64" y="-192" height="192" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin A" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin B" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin up_down" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin ce" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin error" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</graph>
</symbol>

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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="spi_driver">
<symboltype>BLOCK</symboltype>
<timestamp>2016-5-20T8:33:2</timestamp>
<pin polarity="Input" x="0" y="-160" name="clk" />
<pin polarity="Input" x="0" y="-96" name="rst" />
<pin polarity="Input" x="0" y="-32" name="val(11:0)" />
<pin polarity="Output" x="384" y="-160" name="sck" />
<pin polarity="Output" x="384" y="-96" name="cs" />
<pin polarity="Output" x="384" y="-32" name="mosi" />
<graph>
<rect width="256" x="64" y="-192" height="192" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="192" y="-200" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin clk" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin rst" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin val(11:0)" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-160" type="pin sck" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-96" type="pin cs" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="312" y="-32" type="pin mosi" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</graph>
</symbol>

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:51:31 05/17/2016
-- Design Name:
-- Module Name: spi_driver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_driver is
Generic (clk_freq: natural:= 50000000;
adc_res: natural:=12);
Port ( clk : in STD_LOGIC;
rst: in STD_LOGIC;
val : in unsigned (adc_res-1 downto 0);
sck : out STD_LOGIC;
cs : out STD_LOGIC;
mosi : out STD_LOGIC);
end spi_driver;
architecture Behavioral of spi_driver is
type states is(S_IDLE, S_WORK);
signal state_reg, state_next: states := S_IDLE;
signal counter_reg, counter_next: unsigned(5 downto 0) := (others => '0');
signal shift_reg, shift_next: unsigned(19 downto 0):= (others => '0');
begin
REGS: process (clk, rst) is
begin -- process start
if rst = '1' then -- asynchronous reset (active high)
state_reg <= S_IDLE;
counter_reg <= to_unsigned(0,counter_reg'length);
shift_reg <= to_unsigned(0,shift_reg'length);
elsif rising_edge(clk) then -- rising clock edge
state_reg <= state_next;
counter_reg <= counter_next;
shift_reg <= shift_next;
end if;
end process REGS;
mosi <= shift_reg(shift_reg'high) when state_reg=S_WORK else '0';
sck <= '1' when state_reg=S_WORK and counter_reg(0)='1' else '0';
cs <= '1' when state_reg =S_IDLE else '0';
NSL: process (state_reg, counter_reg, shift_reg, val) is
begin
state_next <= state_reg;
counter_next <= counter_reg;
shift_next <= shift_reg;
case state_reg is -- switch on current state
when S_IDLE => -- currently in idle state
state_next <= S_WORK;
counter_next <= to_unsigned(0,counter_reg'length);
shift_next(19 downto 16) <= "0011"; --Command: Write to and Update (Power Up)
shift_next(15 downto 12) <= "0000"; --Adress: DAC0
shift_next(11 downto 0) <= val; -- DAC Value (12bit)
--shift_next(0 downto -3) <= "XXXX"; -- 4x don't care
when S_WORK => -- currently in work state
if(counter_reg = 24*2 -1) then
state_next <= S_IDLE;
else
counter_next<= counter_reg + 1;
end if;
if(counter_reg(0)='1') then
shift_next <= shift_left(shift_reg,1);
end if;
when others => null; -- do nothing, if we are in a different state
end case;
end process NSL;
end Behavioral;

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spi_driver_tb.vhd Normal file
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:38:41 05/17/2016
-- Design Name:
-- Module Name: /home/timo/vhdl-yasg/spi_driver_tb.vhd
-- Project Name: yasg
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_driver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY spi_driver_tb IS
END spi_driver_tb;
ARCHITECTURE behavior OF spi_driver_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT spi_driver
PORT(
clk : IN std_logic;
rst : IN std_logic;
val : IN unsigned(11 downto 0);
sck : OUT std_logic;
cs : OUT std_logic;
mosi : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal val : unsigned(11 downto 0) := (others => '0');
--Outputs
signal sck : std_logic;
signal cs : std_logic;
signal mosi : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns; --50mhz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: spi_driver PORT MAP (
clk => clk,
rst => rst,
val => val,
sck => sck,
cs => cs,
mosi => mosi
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period*10;
val <= to_unsigned(0,12);
wait for clk_period*64;
val <= to_unsigned(7,12);
wait for clk_period*64;
val <= to_unsigned(31,12);
wait for clk_period*64;
val <= to_unsigned(128,12);
wait for clk_period*64;
val <= to_unsigned(512,12);
wait for clk_period*64;
-- insert stimulus here
wait;
end process;
END;

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toplevel.jhd Normal file
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MODULE toplevel
SUBMODULE spi_driver
INSTANCE XLXI_1
SUBMODULE dds
INSTANCE XLXI_2
SUBMODULE controller
INSTANCE XLXI_42
SUBMODULE rotary_dec
INSTANCE XLXI_43

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toplevel.sch Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<drawing version="7">
<attr value="spartan3a" name="DeviceFamilyName">
<trait delete="all:0" />
<trait editname="all:0" />
<trait edittrait="all:0" />
</attr>
<netlist>
<signal name="FORM(1:0)" />
<signal name="FORM(0)" />
<signal name="FORM(1)" />
<signal name="CLK_50MHZ" />
<signal name="XLXN_9(11:0)" />
<signal name="XLXN_10" />
<signal name="SPI_SCK" />
<signal name="DAC_CS" />
<signal name="SPI_MOSI" />
<signal name="FREQ(16:0)" />
<signal name="J18_IO4" />
<signal name="J18_IO2" />
<signal name="J18_IO3" />
<signal name="J18_IO1" />
<signal name="XLXN_30" />
<signal name="DAC_CLR" />
<signal name="LED0" />
<signal name="SW0" />
<signal name="SW1" />
<signal name="XLXN_63" />
<signal name="XLXN_64" />
<signal name="XLXN_65" />
<signal name="XLXN_68" />
<signal name="ROT_A" />
<signal name="ROT_B" />
<signal name="ROT_CENTER" />
<port polarity="Input" name="CLK_50MHZ" />
<port polarity="Output" name="SPI_SCK" />
<port polarity="Output" name="DAC_CS" />
<port polarity="Output" name="SPI_MOSI" />
<port polarity="Output" name="J18_IO4" />
<port polarity="Output" name="J18_IO2" />
<port polarity="Output" name="J18_IO3" />
<port polarity="Output" name="J18_IO1" />
<port polarity="Output" name="DAC_CLR" />
<port polarity="Output" name="LED0" />
<port polarity="Input" name="SW0" />
<port polarity="Input" name="SW1" />
<port polarity="Input" name="ROT_A" />
<port polarity="Input" name="ROT_B" />
<port polarity="Input" name="ROT_CENTER" />
<blockdef name="spi_driver">
<timestamp>2016-5-20T8:33:2</timestamp>
<rect width="256" x="64" y="-192" height="192" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</blockdef>
<blockdef name="dds">
<timestamp>2016-5-20T8:58:58</timestamp>
<rect width="256" x="64" y="-192" height="192" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<rect width="64" x="0" y="-108" height="24" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<rect width="64" x="320" y="-172" height="24" />
<line x2="384" y1="-160" y2="-160" x1="320" />
</blockdef>
<blockdef name="gnd">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-64" y2="-96" x1="64" />
<line x2="52" y1="-48" y2="-48" x1="76" />
<line x2="60" y1="-32" y2="-32" x1="68" />
<line x2="40" y1="-64" y2="-64" x1="88" />
<line x2="64" y1="-64" y2="-80" x1="64" />
<line x2="64" y1="-128" y2="-96" x1="64" />
</blockdef>
<blockdef name="buf">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-32" x1="0" />
<line x2="128" y1="-32" y2="-32" x1="224" />
<line x2="128" y1="0" y2="-32" x1="64" />
<line x2="64" y1="-32" y2="-64" x1="128" />
<line x2="64" y1="-64" y2="0" x1="64" />
</blockdef>
<blockdef name="vcc">
<timestamp>2000-1-1T10:10:10</timestamp>
<line x2="64" y1="-32" y2="-64" x1="64" />
<line x2="64" y1="0" y2="-32" x1="64" />
<line x2="32" y1="-64" y2="-64" x1="96" />
</blockdef>
<blockdef name="controller">
<timestamp>2016-6-3T12:59:50</timestamp>
<line x2="0" y1="-352" y2="-352" x1="64" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<rect width="64" x="368" y="-364" height="24" />
<line x2="432" y1="-352" y2="-352" x1="368" />
<rect width="304" x="64" y="-384" height="384" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
</blockdef>
<blockdef name="rotary_dec">
<timestamp>2016-5-23T16:56:27</timestamp>
<rect width="256" x="64" y="-192" height="192" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="384" y1="-160" y2="-160" x1="320" />
<line x2="384" y1="-96" y2="-96" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" />
</blockdef>
<block symbolname="dds" name="XLXI_2">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="FREQ(16:0)" name="freq(16:0)" />
<blockpin signalname="FORM(1:0)" name="form(1:0)" />
<blockpin signalname="XLXN_9(11:0)" name="amp(11:0)" />
</block>
<block symbolname="spi_driver" name="XLXI_1">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="XLXN_10" name="rst" />
<blockpin signalname="XLXN_9(11:0)" name="val(11:0)" />
<blockpin signalname="SPI_SCK" name="sck" />
<blockpin signalname="DAC_CS" name="cs" />
<blockpin signalname="SPI_MOSI" name="mosi" />
</block>
<block symbolname="gnd" name="XLXI_7">
<blockpin signalname="XLXN_10" name="G" />
</block>
<block symbolname="buf" name="XLXI_14">
<blockpin signalname="SPI_SCK" name="I" />
<blockpin signalname="J18_IO4" name="O" />
</block>
<block symbolname="buf" name="XLXI_15">
<blockpin signalname="DAC_CS" name="I" />
<blockpin signalname="J18_IO2" name="O" />
</block>
<block symbolname="buf" name="XLXI_16">
<blockpin signalname="SPI_MOSI" name="I" />
<blockpin signalname="J18_IO3" name="O" />
</block>
<block symbolname="buf" name="XLXI_17">
<blockpin signalname="CLK_50MHZ" name="I" />
<blockpin signalname="J18_IO1" name="O" />
</block>
<block symbolname="buf" name="XLXI_19">
<blockpin signalname="XLXN_30" name="I" />
<blockpin signalname="DAC_CLR" name="O" />
</block>
<block symbolname="vcc" name="XLXI_20">
<blockpin signalname="XLXN_30" name="P" />
</block>
<block symbolname="buf" name="XLXI_25">
<blockpin signalname="SW0" name="I" />
<blockpin signalname="FORM(0)" name="O" />
</block>
<block symbolname="buf" name="XLXI_26">
<blockpin signalname="SW1" name="I" />
<blockpin signalname="FORM(1)" name="O" />
</block>
<block symbolname="buf" name="XLXI_27">
<blockpin signalname="SW0" name="I" />
<blockpin signalname="LED0" name="O" />
</block>
<block symbolname="controller" name="XLXI_42">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="XLXN_68" name="rst" />
<blockpin signalname="XLXN_63" name="enc_err" />
<blockpin signalname="FREQ(16:0)" name="freq_out(16:0)" />
<blockpin signalname="ROT_CENTER" name="enc_btn" />
<blockpin signalname="XLXN_64" name="enc_ce" />
<blockpin signalname="XLXN_65" name="enc_updown" />
</block>
<block symbolname="rotary_dec" name="XLXI_43">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="ROT_A" name="A" />
<blockpin signalname="ROT_B" name="B" />
<blockpin signalname="XLXN_65" name="up_down" />
<blockpin signalname="XLXN_64" name="ce" />
<blockpin signalname="XLXN_63" name="error" />
</block>
<block symbolname="gnd" name="XLXI_44">
<blockpin signalname="XLXN_68" name="G" />
</block>
</netlist>
<sheet sheetnum="1" width="5440" height="3520">
<instance x="2256" y="1520" name="XLXI_2" orien="R0">
</instance>
<instance x="2848" y="1376" name="XLXI_1" orien="R0">
</instance>
<branch name="FORM(1:0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="2128" y="1488" type="branch" />
<wire x2="2128" y1="1488" y2="1504" x1="2128" />
<wire x2="2128" y1="1504" y2="1536" x1="2128" />
<wire x2="2256" y1="1488" y2="1488" x1="2128" />
</branch>
<bustap x2="2032" y1="1504" y2="1504" x1="2128" />
<bustap x2="2032" y1="1536" y2="1536" x1="2128" />
<branch name="FORM(0)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1936" y="1504" type="branch" />
<wire x2="1936" y1="1504" y2="1504" x1="1824" />
<wire x2="2032" y1="1504" y2="1504" x1="1936" />
</branch>
<branch name="FORM(1)">
<attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="1936" y="1568" type="branch" />
<wire x2="1936" y1="1568" y2="1568" x1="1824" />
<wire x2="2032" y1="1568" y2="1568" x1="1936" />
<wire x2="2032" y1="1536" y2="1568" x1="2032" />
</branch>
<branch name="CLK_50MHZ">
<wire x2="2256" y1="1360" y2="1360" x1="2224" />
</branch>
<branch name="XLXN_9(11:0)">
<wire x2="2736" y1="1360" y2="1360" x1="2640" />
<wire x2="2736" y1="1344" y2="1360" x1="2736" />
<wire x2="2848" y1="1344" y2="1344" x1="2736" />
</branch>
<instance x="2576" y="1264" name="XLXI_7" orien="R0" />
<branch name="XLXN_10">
<wire x2="2640" y1="1072" y2="1136" x1="2640" />
<wire x2="2720" y1="1072" y2="1072" x1="2640" />
<wire x2="2720" y1="1072" y2="1280" x1="2720" />
<wire x2="2848" y1="1280" y2="1280" x1="2720" />
</branch>
<branch name="SPI_SCK">
<wire x2="3264" y1="1216" y2="1216" x1="3232" />
<wire x2="3392" y1="1216" y2="1216" x1="3264" />
<wire x2="3264" y1="1136" y2="1216" x1="3264" />
<wire x2="3392" y1="1136" y2="1136" x1="3264" />
</branch>
<branch name="DAC_CS">
<wire x2="3264" y1="1280" y2="1280" x1="3232" />
<wire x2="3392" y1="1280" y2="1280" x1="3264" />
<wire x2="3264" y1="1248" y2="1280" x1="3264" />
<wire x2="3616" y1="1248" y2="1248" x1="3264" />
</branch>
<branch name="SPI_MOSI">
<wire x2="3264" y1="1344" y2="1344" x1="3232" />
<wire x2="3392" y1="1344" y2="1344" x1="3264" />
<wire x2="3264" y1="1312" y2="1344" x1="3264" />
<wire x2="3616" y1="1312" y2="1312" x1="3264" />
</branch>
<branch name="FREQ(16:0)">
<attrtext style="alignment:SOFT-LEFT;fontsize:28;fontname:Arial" attrname="Name" x="2075" y="1424" type="branch" />
<wire x2="1904" y1="1088" y2="1088" x1="1664" />
<wire x2="1904" y1="1088" y2="1424" x1="1904" />
<wire x2="2256" y1="1424" y2="1424" x1="1904" />
</branch>
<instance x="3392" y="1168" name="XLXI_14" orien="R0" />
<branch name="J18_IO4">
<wire x2="3648" y1="1136" y2="1136" x1="3616" />
</branch>
<instance x="3616" y="1280" name="XLXI_15" orien="R0" />
<instance x="3616" y="1344" name="XLXI_16" orien="R0" />
<branch name="J18_IO2">
<wire x2="3872" y1="1248" y2="1248" x1="3840" />
</branch>
<branch name="J18_IO3">
<wire x2="3872" y1="1312" y2="1312" x1="3840" />
</branch>
<branch name="CLK_50MHZ">
<wire x2="2832" y1="960" y2="960" x1="2784" />
<wire x2="2832" y1="960" y2="1216" x1="2832" />
<wire x2="2848" y1="1216" y2="1216" x1="2832" />
<wire x2="2944" y1="960" y2="960" x1="2832" />
</branch>
<instance x="2944" y="992" name="XLXI_17" orien="R0" />
<branch name="J18_IO1">
<wire x2="3200" y1="960" y2="960" x1="3168" />
</branch>
<instance x="3136" y="1840" name="XLXI_19" orien="R0" />
<branch name="XLXN_30">
<wire x2="3136" y1="1808" y2="1808" x1="3104" />
</branch>
<branch name="DAC_CLR">
<wire x2="3392" y1="1808" y2="1808" x1="3360" />
</branch>
<instance x="3040" y="1808" name="XLXI_20" orien="R0" />
<branch name="LED0">
<wire x2="1872" y1="1648" y2="1648" x1="1824" />
</branch>
<instance x="1600" y="1536" name="XLXI_25" orien="R0" />
<instance x="1600" y="1600" name="XLXI_26" orien="R0" />
<branch name="SW0">
<wire x2="1568" y1="1504" y2="1504" x1="1504" />
<wire x2="1568" y1="1504" y2="1648" x1="1568" />
<wire x2="1600" y1="1648" y2="1648" x1="1568" />
<wire x2="1600" y1="1504" y2="1504" x1="1568" />
</branch>
<branch name="SW1">
<wire x2="1600" y1="1568" y2="1568" x1="1504" />
</branch>
<instance x="1600" y="1680" name="XLXI_27" orien="R0" />
<branch name="XLXN_63">
<wire x2="1232" y1="1408" y2="1408" x1="912" />
</branch>
<branch name="XLXN_64">
<wire x2="1232" y1="1344" y2="1344" x1="912" />
</branch>
<branch name="XLXN_65">
<wire x2="1232" y1="1280" y2="1280" x1="912" />
</branch>
<iomarker fontsize="28" x="2224" y="1360" name="CLK_50MHZ" orien="R180" />
<iomarker fontsize="28" x="3392" y="1216" name="SPI_SCK" orien="R0" />
<iomarker fontsize="28" x="3392" y="1280" name="DAC_CS" orien="R0" />
<iomarker fontsize="28" x="3392" y="1344" name="SPI_MOSI" orien="R0" />
<iomarker fontsize="28" x="3872" y="1248" name="J18_IO2" orien="R0" />
<iomarker fontsize="28" x="3872" y="1312" name="J18_IO3" orien="R0" />
<iomarker fontsize="28" x="3200" y="960" name="J18_IO1" orien="R0" />
<iomarker fontsize="28" x="3648" y="1136" name="J18_IO4" orien="R0" />
<iomarker fontsize="28" x="2784" y="960" name="CLK_50MHZ" orien="R180" />
<iomarker fontsize="28" x="3392" y="1808" name="DAC_CLR" orien="R0" />
<iomarker fontsize="28" x="1872" y="1648" name="LED0" orien="R0" />
<iomarker fontsize="28" x="1504" y="1568" name="SW1" orien="R180" />
<iomarker fontsize="28" x="1504" y="1504" name="SW0" orien="R180" />
<instance x="1232" y="1440" name="XLXI_42" orien="R0">
</instance>
<branch name="CLK_50MHZ">
<wire x2="1216" y1="880" y2="880" x1="1152" />
<wire x2="1216" y1="880" y2="1088" x1="1216" />
<wire x2="1232" y1="1088" y2="1088" x1="1216" />
</branch>
<iomarker fontsize="28" x="1152" y="880" name="CLK_50MHZ" orien="R180" />
<instance x="528" y="1440" name="XLXI_43" orien="R0">
</instance>
<branch name="ROT_A">
<wire x2="528" y1="1344" y2="1344" x1="496" />
</branch>
<branch name="ROT_B">
<wire x2="528" y1="1408" y2="1408" x1="496" />
</branch>
<branch name="CLK_50MHZ">
<wire x2="528" y1="1280" y2="1280" x1="496" />
</branch>
<iomarker fontsize="28" x="496" y="1344" name="ROT_A" orien="R180" />
<iomarker fontsize="28" x="496" y="1408" name="ROT_B" orien="R180" />
<iomarker fontsize="28" x="496" y="1280" name="CLK_50MHZ" orien="R180" />
<instance x="1040" y="1120" name="XLXI_44" orien="R0" />
<branch name="XLXN_68">
<wire x2="1184" y1="992" y2="992" x1="1104" />
<wire x2="1184" y1="992" y2="1152" x1="1184" />
<wire x2="1232" y1="1152" y2="1152" x1="1184" />
</branch>
<branch name="ROT_CENTER">
<wire x2="1232" y1="1216" y2="1216" x1="1200" />
</branch>
<iomarker fontsize="28" x="1200" y="1216" name="ROT_CENTER" orien="R180" />
</sheet>
</drawing>

365
yasg.gise
View File

@@ -30,55 +30,113 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="controller.prj"/>
<file xil_pn:fileType="FILE_SPL" xil_pn:name="controller.spl"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="controller.stx"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="controller.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="controller.xst"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="dds.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="dds.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="dds.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="dds.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="dds.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="dds.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="dds.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="dds.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="dds.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds.prj"/>
<file xil_pn:fileType="FILE_SPL" xil_pn:name="dds.spl"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="dds.stx"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="dds.sym" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="dds.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="dds.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="dds.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="dds.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="dds.vhi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="dds.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="dds_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="dds_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="dds_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="dds_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="dds_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="dds_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="dds_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="dds_summary.html"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="dds_tb_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="dds_tb_isim_beh.wdb"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_tb_stx_beh.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="dds_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="dds_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="lcd_driver.bgn" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="lcd_driver.bit" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="lcd_driver.bld"/> <file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="lcd_driver.cmd_log"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="rotary_dec.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="lcd_driver.drc" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:fileType="FILE_SPL" xil_pn:name="rotary_dec.spl"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="lcd_driver.lso"/> <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="rotary_dec.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="lcd_driver.ncd" xil_pn:subbranch="Par"/> <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="rotary_dec.sym" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="lcd_driver.ngc"/> <file xil_pn:fileType="FILE_XST" xil_pn:name="rotary_dec.xst"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="lcd_driver.ngd"/> <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="spi_driver.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="lcd_driver.ngr"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="spi_driver.lso"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="lcd_driver.pad"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="spi_driver.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="lcd_driver.par" xil_pn:subbranch="Par"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="spi_driver.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="lcd_driver.pcf" xil_pn:subbranch="Map"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="spi_driver.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/> <file xil_pn:fileType="FILE_SPL" xil_pn:name="spi_driver.spl"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="lcd_driver.ptwx"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="spi_driver.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/> <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="spi_driver.sym" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="lcd_driver.syr"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="spi_driver.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="lcd_driver.twr" xil_pn:subbranch="Par"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="spi_driver.xst"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="lcd_driver.twx" xil_pn:subbranch="Par"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_envsettings.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="lcd_driver.unroutes" xil_pn:subbranch="Par"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="lcd_driver.ut" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="spi_driver_summary.html"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="lcd_driver.xpi"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="spi_driver_tb_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/> <file xil_pn:fileType="FILE_XRPT" xil_pn:name="spi_driver_xst.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="lcd_driver_envsettings.html"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="toplevel.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="lcd_driver_guide.ncd" xil_pn:origination="imported"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="toplevel.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="lcd_driver_isim_beh.exe"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="toplevel.bld"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="lcd_driver_map.map" xil_pn:subbranch="Map"/> <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="toplevel.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="lcd_driver_map.mrp" xil_pn:subbranch="Map"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="toplevel.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="lcd_driver_map.ncd" xil_pn:subbranch="Map"/> <file xil_pn:fileType="FILE_JHD" xil_pn:name="toplevel.jhd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="lcd_driver_map.ngm" xil_pn:subbranch="Map"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="toplevel.lso"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="lcd_driver_map.xrpt"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="toplevel.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="lcd_driver_ngdbuild.xrpt"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="toplevel.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="lcd_driver_pad.csv" xil_pn:subbranch="Par"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="toplevel.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="lcd_driver_pad.txt" xil_pn:subbranch="Par"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="toplevel.ngr"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="lcd_driver_par.xrpt"/> <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="toplevel.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver_stx_beh.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="toplevel.par" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="lcd_driver_summary.html"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="toplevel.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="lcd_driver_summary.xml"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="toplevel.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver_tb_beh.prj"/> <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="toplevel.ptwx"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="lcd_driver_tb_isim_beh.exe"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="toplevel.stx"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="lcd_driver_tb_isim_beh.wdb"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="toplevel.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver_tb_stx_beh.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="toplevel.twr" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="lcd_driver_usage.xml"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="toplevel.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver_vhdl.prj"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="toplevel.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="lcd_driver_xst.xrpt"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="toplevel.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="toplevel.vhf"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="toplevel.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="toplevel.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="toplevel_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="toplevel_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="toplevel_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="toplevel_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="toplevel_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="toplevel_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="toplevel_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="toplevel_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="toplevel_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="toplevel_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="toplevel_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="toplevel_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="toplevel_xst.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/> <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/> <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
@@ -88,167 +146,214 @@
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1463425900" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1463425900"> <transform xil_pn:end_ts="1463390579" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1463390579">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1464963520" xil_pn:in_ck="4963174131653437457" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1464963520"> <transform xil_pn:end_ts="1464953958" xil_pn:in_ck="7359381923225456452" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1464953958">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="lcd_driver.vhd"/>
<outfile xil_pn:name="lcd_driver_tb.vhd"/>
</transform>
<transform xil_pn:end_ts="1464956616" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2560282312695158014" xil_pn:start_ts="1464956616">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1464956616" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="2072151057923631594" xil_pn:start_ts="1464956616">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1463425900" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8001612460604873661" xil_pn:start_ts="1463425900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1464963540" xil_pn:in_ck="4963174131653437457" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1464963540">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="lcd_driver.vhd"/>
<outfile xil_pn:name="lcd_driver_tb.vhd"/>
</transform>
<transform xil_pn:end_ts="1464963542" xil_pn:in_ck="4963174131653437457" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8378225353365721463" xil_pn:start_ts="1464963540">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="controller.vhd"/>
<outfile xil_pn:name="dds.vhd"/>
<outfile xil_pn:name="dds_tb.vhd"/>
<outfile xil_pn:name="helpers.vhd"/>
<outfile xil_pn:name="lcd_driver.vhd"/>
<outfile xil_pn:name="rotary.vhd"/>
<outfile xil_pn:name="spi_driver.vhd"/>
<outfile xil_pn:name="spi_driver_tb.vhd"/>
</transform>
<transform xil_pn:end_ts="1464093026" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8944967924106743327" xil_pn:start_ts="1464093026">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1464093027" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="5140074775533282471" xil_pn:start_ts="1464093026">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1464081246" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1464081246">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1464953958" xil_pn:in_ck="7359381923225456452" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1464953958">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="controller.vhd"/>
<outfile xil_pn:name="dds.vhd"/>
<outfile xil_pn:name="dds_tb.vhd"/>
<outfile xil_pn:name="helpers.vhd"/>
<outfile xil_pn:name="lcd_driver.vhd"/>
<outfile xil_pn:name="rotary.vhd"/>
<outfile xil_pn:name="spi_driver.vhd"/>
<outfile xil_pn:name="spi_driver_tb.vhd"/>
</transform>
<transform xil_pn:end_ts="1464953960" xil_pn:in_ck="7359381923225456452" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6917596232395121981" xil_pn:start_ts="1464953958">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="dds_tb_beh.prj"/>
<outfile xil_pn:name="dds_tb_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/> <outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/> <outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="lcd_driver_tb_beh.prj"/>
<outfile xil_pn:name="lcd_driver_tb_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/> <outfile xil_pn:name="xilinxsim.ini"/>
</transform> </transform>
<transform xil_pn:end_ts="1464963542" xil_pn:in_ck="-1249634404730829457" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-890565599326071882" xil_pn:start_ts="1464963542"> <transform xil_pn:end_ts="1464954092" xil_pn:in_ck="-1222633688712987584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1464954092">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="dds_tb_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/> <outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="lcd_driver_tb_isim_beh.wdb"/>
</transform> </transform>
<transform xil_pn:end_ts="1463411472" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1463411472"> <transform xil_pn:end_ts="1464958322" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1464958322">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463411472" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="576887694218117698" xil_pn:start_ts="1463411472"> <transform xil_pn:end_ts="1464958805" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1464958803">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<outfile xil_pn:name="toplevel.vhf"/>
</transform>
<transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463411472" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8001612460604873661" xil_pn:start_ts="1463411472"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463411472" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1463411472"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2239360189155701135" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1463411472" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="8718783841148945690" xil_pn:start_ts="1463411472"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1463411472" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1463411472"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7072966905182239268" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1463411472" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3195098281710583859" xil_pn:start_ts="1463411472"> <transform xil_pn:end_ts="1464959693" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1464959680">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1464963648" xil_pn:in_ck="8811521640337194126" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="2199470219804545175" xil_pn:start_ts="1464963642">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name=".lso"/> <outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="lcd_driver.lso"/> <outfile xil_pn:name="dds.ngr"/>
<outfile xil_pn:name="lcd_driver.ngc"/> <outfile xil_pn:name="spi_driver.ngr"/>
<outfile xil_pn:name="lcd_driver.ngr"/> <outfile xil_pn:name="toplevel.jhd"/>
<outfile xil_pn:name="lcd_driver.prj"/> <outfile xil_pn:name="toplevel.lso"/>
<outfile xil_pn:name="lcd_driver.stx"/> <outfile xil_pn:name="toplevel.ngc"/>
<outfile xil_pn:name="lcd_driver.syr"/> <outfile xil_pn:name="toplevel.ngr"/>
<outfile xil_pn:name="lcd_driver.xst"/> <outfile xil_pn:name="toplevel.prj"/>
<outfile xil_pn:name="lcd_driver_stx_beh.prj"/> <outfile xil_pn:name="toplevel.stx"/>
<outfile xil_pn:name="lcd_driver_tb_beh.prj"/> <outfile xil_pn:name="toplevel.syr"/>
<outfile xil_pn:name="lcd_driver_tb_stx_beh.prj"/> <outfile xil_pn:name="toplevel.xst"/>
<outfile xil_pn:name="lcd_driver_xst.xrpt"/> <outfile xil_pn:name="toplevel_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1464949746" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3272221434217320822" xil_pn:start_ts="1464949746"> <transform xil_pn:end_ts="1464958336" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1464958336">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1464963656" xil_pn:in_ck="8811521640337185380" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1770289617007127622" xil_pn:start_ts="1464963653"> <transform xil_pn:end_ts="1464959698" xil_pn:in_ck="2169537708537049843" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1464959693">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="lcd_driver.bld"/> <outfile xil_pn:name="toplevel.bld"/>
<outfile xil_pn:name="lcd_driver.ngd"/> <outfile xil_pn:name="toplevel.ngd"/>
<outfile xil_pn:name="lcd_driver_ngdbuild.xrpt"/> <outfile xil_pn:name="toplevel_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1464963661" xil_pn:in_ck="8811521640337185381" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1464963656"> <transform xil_pn:end_ts="1464959705" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1464959698">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="lcd_driver.pcf"/> <outfile xil_pn:name="toplevel.pcf"/>
<outfile xil_pn:name="lcd_driver_map.map"/> <outfile xil_pn:name="toplevel_map.map"/>
<outfile xil_pn:name="lcd_driver_map.mrp"/> <outfile xil_pn:name="toplevel_map.mrp"/>
<outfile xil_pn:name="lcd_driver_map.ncd"/> <outfile xil_pn:name="toplevel_map.ncd"/>
<outfile xil_pn:name="lcd_driver_map.ngm"/> <outfile xil_pn:name="toplevel_map.ngm"/>
<outfile xil_pn:name="lcd_driver_map.xrpt"/> <outfile xil_pn:name="toplevel_map.xrpt"/>
<outfile xil_pn:name="lcd_driver_summary.xml"/> <outfile xil_pn:name="toplevel_summary.xml"/>
<outfile xil_pn:name="lcd_driver_usage.xml"/> <outfile xil_pn:name="toplevel_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1464963675" xil_pn:in_ck="1632125194089567230" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1464963661"> <transform xil_pn:end_ts="1464959723" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1464959705">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="lcd_driver.ncd"/> <outfile xil_pn:name="toplevel.ncd"/>
<outfile xil_pn:name="lcd_driver.pad"/> <outfile xil_pn:name="toplevel.pad"/>
<outfile xil_pn:name="lcd_driver.par"/> <outfile xil_pn:name="toplevel.par"/>
<outfile xil_pn:name="lcd_driver.ptwx"/> <outfile xil_pn:name="toplevel.ptwx"/>
<outfile xil_pn:name="lcd_driver.unroutes"/> <outfile xil_pn:name="toplevel.unroutes"/>
<outfile xil_pn:name="lcd_driver.xpi"/> <outfile xil_pn:name="toplevel.xpi"/>
<outfile xil_pn:name="lcd_driver_pad.csv"/> <outfile xil_pn:name="toplevel_pad.csv"/>
<outfile xil_pn:name="lcd_driver_pad.txt"/> <outfile xil_pn:name="toplevel_pad.txt"/>
<outfile xil_pn:name="lcd_driver_par.xrpt"/> <outfile xil_pn:name="toplevel_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1464963684" xil_pn:in_ck="8811521640337185249" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1464963679"> <transform xil_pn:end_ts="1464959731" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1464959723">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="lcd_driver.bgn"/> <outfile xil_pn:name="toplevel.bgn"/>
<outfile xil_pn:name="lcd_driver.bit"/> <outfile xil_pn:name="toplevel.bit"/>
<outfile xil_pn:name="lcd_driver.drc"/> <outfile xil_pn:name="toplevel.drc"/>
<outfile xil_pn:name="lcd_driver.ut"/> <outfile xil_pn:name="toplevel.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/> <outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1464963692" xil_pn:in_ck="8811521640337172395" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1464963691"> <transform xil_pn:end_ts="1464955208" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1464955207">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1464963675" xil_pn:in_ck="8811521640337185249" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1464963673"> <transform xil_pn:end_ts="1464959723" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1464959719">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="lcd_driver.twr"/> <outfile xil_pn:name="toplevel.twr"/>
<outfile xil_pn:name="lcd_driver.twx"/> <outfile xil_pn:name="toplevel.twx"/>
</transform> </transform>
</transforms> </transforms>

65
yasg.xise
View File

@@ -16,38 +16,79 @@
<files> <files>
<file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="dds_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="spi_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="spi_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="toplevel.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="io.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="rotary.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="17"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="17"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="17"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="132"/>
</file> </file>
</files> </files>
<properties> <properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/> <property xil_pn:name="Device" xil_pn:value="xc3s700an" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3AN Starter Kit" xil_pn:valueState="non-default"/> <property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3AN Starter Kit" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|lcd_driver|Behavioral" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Module|toplevel" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="lcd_driver.vhd" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="toplevel.sch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/lcd_driver" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/toplevel" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/> <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/lcd_driver_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/dds_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.lcd_driver_tb" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.dds_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic" xil_pn:valueState="non-default"/> <property xil_pn:name="Top-Level Source Type" xil_pn:value="Schematic" xil_pn:valueState="non-default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|lcd_driver_tb|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|dds_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="yasg" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-05-09T19:06:02" xil_pn:valueState="non-default"/>
@@ -56,7 +97,9 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties> </properties>
<bindings/> <bindings>
<binding xil_pn:location="/toplevel" xil_pn:name="io.ucf"/>
</bindings>
<libraries/> <libraries/>