diff --git a/.gitignore b/.gitignore
index 72e9bfc..857ec81 100644
--- a/.gitignore
+++ b/.gitignore
@@ -14,3 +14,4 @@
!*.wcfg
!*/
!documentation/*
+!screenshots/*
diff --git a/controller.sym b/controller.sym
new file mode 100644
index 0000000..f90185d
--- /dev/null
+++ b/controller.sym
@@ -0,0 +1,31 @@
+
+
+ BLOCK
+ 2016-6-3T12:59:50
+
+
+
+
+
+
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+
+
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diff --git a/controller.vhd b/controller.vhd
new file mode 100644
index 0000000..3f6bcfb
--- /dev/null
+++ b/controller.vhd
@@ -0,0 +1,94 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 18:47:36 05/23/2016
+-- Design Name:
+-- Module Name: controller - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity controller is
+ Port ( clk : in STD_LOGIC;
+ rst: in STD_LOGIC;
+ enc_updown : in STD_LOGIC;
+ enc_ce : in STD_LOGIC;
+ enc_btn: in STD_LOGIC;
+ enc_err : in STD_LOGIC;
+ freq_out : out unsigned (16 downto 0));
+end controller;
+
+architecture Behavioral of controller is
+ signal freq_reg, freq_next : unsigned(16 downto 0) := to_unsigned(1000,17);
+ signal digpos_reg, digpos_next : unsigned(2 downto 0) := to_unsigned(0,3);
+ signal btn_old_reg, btn_old_next : std_logic := '0';
+
+ type storage is array (4 downto 0) of unsigned (16 downto 0);
+ constant bases : storage := (to_unsigned(1,17),to_unsigned(10,17),
+ to_unsigned(100,17),to_unsigned(1000,17),
+ to_unsigned(10000,17));
+
+ signal digpos_base : unsigned(16 downto 0);
+begin
+
+ proc1: process(clk,rst)
+ begin
+ if(rst='1') then
+ freq_reg <= to_unsigned(1000,17);
+ digpos_reg <= to_unsigned(0,3);
+ btn_old_reg <= '0';
+ elsif(rising_edge(clk)) then
+ freq_reg <= freq_next;
+ digpos_reg <= digpos_next;
+ btn_old_reg <= btn_old_next;
+ end if;
+ end process proc1;
+
+ freq_out <= freq_reg;
+ digpos_base <= bases(to_integer(digpos_reg));
+
+ proc2: process(freq_reg,enc_updown,enc_ce,enc_err,enc_btn,digpos_reg,digpos_base,btn_old_reg)
+ begin
+ freq_next <= freq_reg;
+ digpos_next <= digpos_reg;
+ btn_old_next <= enc_btn;
+
+ if(enc_ce='1' and enc_err='0') then
+ if(enc_updown='1') then
+ freq_next <= freq_reg + digpos_base;
+ else
+ freq_next <= freq_reg - digpos_base;
+ end if;
+ elsif(enc_btn ='1' and btn_old_reg='0') then
+ if(digpos_reg = to_unsigned(4,3)) then
+ digpos_next <= to_unsigned(0,3);
+ else
+ digpos_next <= digpos_reg + 1;
+ end if;
+ end if;
+
+ end process proc2;
+
+end Behavioral;
+
diff --git a/dds.sym b/dds.sym
new file mode 100644
index 0000000..e0064ee
--- /dev/null
+++ b/dds.sym
@@ -0,0 +1,24 @@
+
+
+ BLOCK
+ 2016-5-20T8:58:58
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/dds.vhd b/dds.vhd
new file mode 100644
index 0000000..9512513
--- /dev/null
+++ b/dds.vhd
@@ -0,0 +1,101 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:09:53 05/16/2016
+-- Design Name:
+-- Module Name: dds - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.MATH_REAL.ALL;
+use work.helpers.all;
+
+entity dds is
+ Generic (clk_freq: natural:= 50000000;
+ freq_res: natural:=17; -- width of frequency input (log2(max_freq))
+ adc_res: natural:=12; -- width of the ouput signal (=adc resolution)
+ acc_res: natural:=32; -- width of the phase accumulator
+ phase_res: natural:=10); -- effective phase resolution for sin lookup table
+ Port ( clk : in STD_LOGIC;
+ freq : in unsigned (freq_res-1 downto 0);
+ form : in unsigned (1 downto 0);
+ amp : out unsigned (adc_res-1 downto 0));
+end dds;
+
+architecture Behavioral of dds is
+ signal m, idx : unsigned(acc_res -1 downto 0):= (others => '0');
+ signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0');
+ signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0);
+
+ type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0);
+ --type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
+ function gen_sin_wave return storage is
+ variable temp : storage;
+ begin
+ forLoop: for i in 0 to temp'high loop
+ temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1);
+ --temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1) + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);
+
+ end loop;
+ return temp;
+ end function gen_sin_wave;
+ constant sin_wave : storage := gen_sin_wave;
+
+begin
+
+ -- m = fout*(2^n)/fclk = fout*((2^n)*(2^k)/fclk)/(2^k) with k=ceil(log2(fclk)), n=acc_res
+ m <= resize( (resize(freq,64)
+ *
+ (shift_left(to_unsigned(1,64),acc_res + log2_int(clk_freq)) / clk_freq))
+ /to_unsigned(2**log2_int(clk_freq),64),acc_res);
+
+
+ amp_rect <= to_unsigned(0,adc_res) when idx(acc_res-1)='0' else
+ to_unsigned((2**adc_res)-1,adc_res);
+
+ amp_saw <= idx(acc_res -1 downto acc_res - adc_res);
+
+
+ amp_tria <= idx(acc_res -2 downto acc_res - adc_res) & "0"
+ when idx(acc_res-1)='0' else
+ ((2**adc_res)-1)- (idx(acc_res -2 downto acc_res - adc_res) & "0");
+
+
+
+ idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
+
+ --amp_sin <= sin_wave(to_integer(idx_phase));
+ amp_sin <= to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="00" else
+ to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="01" else
+ to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(idx_phase(phase_res-3 downto 0))) when idx_phase(phase_res-1 downto phase_res-2)="10" else
+ to_unsigned((2**(adc_res-1)) - 1,adc_res) - sin_wave(to_integer(((2**(phase_res-2))-1) - idx_phase(phase_res-3 downto 0)));
+
+
+ with form select amp <= amp_rect when "00",
+ amp_saw when "01",
+ amp_tria when "10",
+ amp_sin when others;
+
+ P1: process(clk)
+ begin
+ if(rising_edge(clk)) then
+ idx <= (idx+m);
+ end if;
+ end process P1;
+
+
+end Behavioral;
+
diff --git a/dds_tb.vhd b/dds_tb.vhd
new file mode 100644
index 0000000..73b1259
--- /dev/null
+++ b/dds_tb.vhd
@@ -0,0 +1,116 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 11:35:57 05/16/2016
+-- Design Name:
+-- Module Name: /home/timo/vhdl-yasg/dds_tb.vhd
+-- Project Name: yasg
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: dds
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY dds_tb IS
+END dds_tb;
+
+ARCHITECTURE behavior OF dds_tb IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT dds
+ PORT(
+ clk : IN std_logic;
+ freq : IN unsigned(16 downto 0);
+ form : IN unsigned(1 downto 0);
+ amp : OUT unsigned(11 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal freq : unsigned(16 downto 0) := (others => '0');
+ signal form : unsigned(1 downto 0) := (others => '0');
+
+ --Outputs
+ signal amp : unsigned(11 downto 0);
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns; --50mhz
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: dds PORT MAP (
+ clk => clk,
+ freq => freq,
+ form => form,
+ amp => amp
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+
+
+ form <= "00";
+ freq <= to_unsigned(50000,17);
+ wait for 40 us;
+ freq <= to_unsigned(100000,17);
+ wait for 20 us;
+
+ form <= "01";
+ freq <= to_unsigned(50000,17);
+ wait for 40 us;
+ freq <= to_unsigned(100000,17);
+ wait for 20 us;
+
+ form <= "10";
+ freq <= to_unsigned(50000,17);
+ wait for 40 us;
+ freq <= to_unsigned(100000,17);
+ wait for 20 us;
+
+ form <= "11";
+ freq <= to_unsigned(50000,17);
+ wait for 40 us;
+ freq <= to_unsigned(100000,17);
+ wait for 20 us;
+
+
+ wait;
+ end process;
+
+END;
diff --git a/helpers.vhd b/helpers.vhd
new file mode 100644
index 0000000..b0e3105
--- /dev/null
+++ b/helpers.vhd
@@ -0,0 +1,46 @@
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+package helpers is
+ --helper function to calculate the log2 (truncated) of a integer
+ function log2_int(n:natural) return natural;
+ function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
+end helpers;
+
+
+
+package body helpers is
+ function log2_int(n:natural) return natural is
+ begin
+ if(n>1) then --we can stil divide n by 2
+ return 1+log2_int(n/2); --recursivly call log2_int for the by two divided number.
+ end if;
+ return 1; --since we can no longer divide n, return 1
+ end log2_int;
+
+ --Source: http://vhdlguru.blogspot.ch/2010/03/vhdl-function-for-division-two-signed.html
+ function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
+ variable a1 : unsigned(a'length-1 downto 0):=a;
+ variable b1 : unsigned(b'length-1 downto 0):=b;
+ variable p1 : unsigned(b'length downto 0):= (others => '0');
+ variable i : integer:=0;
+
+ begin
+ for i in 0 to b'length-1 loop
+ p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
+ p1(0) := a1(a'length-1);
+ a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
+ p1 := p1-b1;
+ if(p1(b'length-1) ='1') then
+ a1(0) :='0';
+ p1 := p1+b1;
+ else
+ a1(0) :='1';
+ end if;
+ end loop;
+ return a1;
+ end divide;
+end helpers;
+
diff --git a/io.ucf b/io.ucf
new file mode 100644
index 0000000..e441457
--- /dev/null
+++ b/io.ucf
@@ -0,0 +1,24 @@
+NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
+NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
+
+
+NET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "DAC_CS" LOC = "W7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "DAC_CLR" LOC = "AB13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "DAC_OUT" LOC = "V7" | IOSTANDARD = LVCMOS33
+
+
+NET "J18_IO1" LOC = "AA21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "J18_IO2" LOC = "AB21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "J18_IO3" LOC = "AA19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "J18_IO4" LOC = "AB19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+
+NET "LED0" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+NET "SW0" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
+NET "SW1" LOC = "U10"| IOSTANDARD = LVCMOS33 ;
+
+NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN;
+
\ No newline at end of file
diff --git a/rotary.vhd b/rotary.vhd
new file mode 100644
index 0000000..ca11399
--- /dev/null
+++ b/rotary.vhd
@@ -0,0 +1,65 @@
+-----------------------------------------------------------------------------
+--
+-- Decoder für Drehgeber
+--
+-----------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity rotary_dec is
+ Port ( clk : in std_logic; -- Systemtakt
+ A : in std_logic; -- Spur A
+ B : in std_logic; -- Spur B
+ up_down : out std_logic; -- Zaehlrichtung
+ ce : out std_logic; -- Clock Enable
+ error : out std_logic); -- illegaler Signalübergang
+end rotary_dec;
+
+architecture Behavioral of rotary_dec is
+
+signal a_in, b_in, a_old, b_old: std_logic;
+
+begin
+
+-- Abtastung und Verzoegerung der Quadratursignale
+
+process(clk)
+begin
+ if rising_edge(clk) then
+ a_old <= a_in;
+ a_in <= A;
+ b_old <= b_in;
+ b_in <= B;
+ end if;
+end process;
+
+-- Dekodierung der Ausgaenge
+
+process(a_in, b_in, a_old, b_old)
+variable state: std_logic_vector(3 downto 0);
+begin
+ state := a_in & b_in & a_old & b_old;
+ case state is
+ when "0000" => up_down <= '0'; ce <= '0'; error <= '0';
+ when "0001" => up_down <= '1'; ce <= '1'; error <= '0';
+ when "0010" => up_down <= '0'; ce <= '1'; error <= '0';
+ when "0011" => up_down <= '0'; ce <= '0'; error <= '1';
+ when "0100" => up_down <= '0'; ce <= '1'; error <= '0';
+ when "0101" => up_down <= '0'; ce <= '0'; error <= '0';
+ when "0110" => up_down <= '0'; ce <= '0'; error <= '1';
+ when "0111" => up_down <= '1'; ce <= '1'; error <= '0';
+ when "1000" => up_down <= '1'; ce <= '1'; error <= '0';
+ when "1001" => up_down <= '0'; ce <= '0'; error <= '1';
+ when "1010" => up_down <= '0'; ce <= '0'; error <= '0';
+ when "1011" => up_down <= '0'; ce <= '1'; error <= '0';
+ when "1100" => up_down <= '0'; ce <= '0'; error <= '1';
+ when "1101" => up_down <= '0'; ce <= '1'; error <= '0';
+ when "1110" => up_down <= '1'; ce <= '1'; error <= '0';
+ when "1111" => up_down <= '0'; ce <= '0'; error <= '0';
+ when others => null;
+ end case;
+end process;
+
+end Behavioral;
+
diff --git a/rotary_dec.sym b/rotary_dec.sym
new file mode 100644
index 0000000..f48b8dc
--- /dev/null
+++ b/rotary_dec.sym
@@ -0,0 +1,27 @@
+
+
+ BLOCK
+ 2016-5-23T16:56:27
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/screenshots/V9-Nr2.png b/screenshots/V9-Nr2.png
new file mode 100755
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diff --git a/screenshots/V9-Nr3.png b/screenshots/V9-Nr3.png
new file mode 100755
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diff --git a/screenshots/V9-Nr4.png b/screenshots/V9-Nr4.png
new file mode 100755
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diff --git a/spi_driver.sym b/spi_driver.sym
new file mode 100644
index 0000000..9bd3cd8
--- /dev/null
+++ b/spi_driver.sym
@@ -0,0 +1,28 @@
+
+
+ BLOCK
+ 2016-5-20T8:33:2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/spi_driver.vhd b/spi_driver.vhd
new file mode 100644
index 0000000..582de95
--- /dev/null
+++ b/spi_driver.vhd
@@ -0,0 +1,92 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:51:31 05/17/2016
+-- Design Name:
+-- Module Name: spi_driver - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity spi_driver is
+ Generic (clk_freq: natural:= 50000000;
+ adc_res: natural:=12);
+ Port ( clk : in STD_LOGIC;
+ rst: in STD_LOGIC;
+ val : in unsigned (adc_res-1 downto 0);
+ sck : out STD_LOGIC;
+ cs : out STD_LOGIC;
+ mosi : out STD_LOGIC);
+end spi_driver;
+
+architecture Behavioral of spi_driver is
+ type states is(S_IDLE, S_WORK);
+ signal state_reg, state_next: states := S_IDLE;
+ signal counter_reg, counter_next: unsigned(5 downto 0) := (others => '0');
+ signal shift_reg, shift_next: unsigned(19 downto 0):= (others => '0');
+begin
+ REGS: process (clk, rst) is
+ begin -- process start
+ if rst = '1' then -- asynchronous reset (active high)
+ state_reg <= S_IDLE;
+ counter_reg <= to_unsigned(0,counter_reg'length);
+ shift_reg <= to_unsigned(0,shift_reg'length);
+ elsif rising_edge(clk) then -- rising clock edge
+ state_reg <= state_next;
+ counter_reg <= counter_next;
+ shift_reg <= shift_next;
+ end if;
+ end process REGS;
+
+ mosi <= shift_reg(shift_reg'high) when state_reg=S_WORK else '0';
+ sck <= '1' when state_reg=S_WORK and counter_reg(0)='1' else '0';
+ cs <= '1' when state_reg =S_IDLE else '0';
+
+ NSL: process (state_reg, counter_reg, shift_reg, val) is
+ begin
+ state_next <= state_reg;
+ counter_next <= counter_reg;
+ shift_next <= shift_reg;
+ case state_reg is -- switch on current state
+ when S_IDLE => -- currently in idle state
+ state_next <= S_WORK;
+ counter_next <= to_unsigned(0,counter_reg'length);
+
+ shift_next(19 downto 16) <= "0011"; --Command: Write to and Update (Power Up)
+ shift_next(15 downto 12) <= "0000"; --Adress: DAC0
+ shift_next(11 downto 0) <= val; -- DAC Value (12bit)
+ --shift_next(0 downto -3) <= "XXXX"; -- 4x don't care
+
+ when S_WORK => -- currently in work state
+ if(counter_reg = 24*2 -1) then
+ state_next <= S_IDLE;
+ else
+ counter_next<= counter_reg + 1;
+ end if;
+ if(counter_reg(0)='1') then
+ shift_next <= shift_left(shift_reg,1);
+ end if;
+ when others => null; -- do nothing, if we are in a different state
+ end case;
+ end process NSL;
+
+end Behavioral;
+
diff --git a/spi_driver_tb.vhd b/spi_driver_tb.vhd
new file mode 100644
index 0000000..a8c72b3
--- /dev/null
+++ b/spi_driver_tb.vhd
@@ -0,0 +1,118 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:38:41 05/17/2016
+-- Design Name:
+-- Module Name: /home/timo/vhdl-yasg/spi_driver_tb.vhd
+-- Project Name: yasg
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: spi_driver
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY spi_driver_tb IS
+END spi_driver_tb;
+
+ARCHITECTURE behavior OF spi_driver_tb IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT spi_driver
+ PORT(
+ clk : IN std_logic;
+ rst : IN std_logic;
+ val : IN unsigned(11 downto 0);
+ sck : OUT std_logic;
+ cs : OUT std_logic;
+ mosi : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk : std_logic := '0';
+ signal rst : std_logic := '0';
+ signal val : unsigned(11 downto 0) := (others => '0');
+
+ --Outputs
+ signal sck : std_logic;
+ signal cs : std_logic;
+ signal mosi : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := 20 ns; --50mhz
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: spi_driver PORT MAP (
+ clk => clk,
+ rst => rst,
+ val => val,
+ sck => sck,
+ cs => cs,
+ mosi => mosi
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ rst <= '1';
+ wait for 100 ns;
+ rst <= '0';
+ wait for clk_period*10;
+
+ val <= to_unsigned(0,12);
+ wait for clk_period*64;
+
+ val <= to_unsigned(7,12);
+ wait for clk_period*64;
+
+ val <= to_unsigned(31,12);
+ wait for clk_period*64;
+
+ val <= to_unsigned(128,12);
+ wait for clk_period*64;
+
+ val <= to_unsigned(512,12);
+ wait for clk_period*64;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/toplevel.jhd b/toplevel.jhd
new file mode 100644
index 0000000..d1c361a
--- /dev/null
+++ b/toplevel.jhd
@@ -0,0 +1,9 @@
+MODULE toplevel
+ SUBMODULE spi_driver
+ INSTANCE XLXI_1
+ SUBMODULE dds
+ INSTANCE XLXI_2
+ SUBMODULE controller
+ INSTANCE XLXI_42
+ SUBMODULE rotary_dec
+ INSTANCE XLXI_43
diff --git a/toplevel.sch b/toplevel.sch
new file mode 100644
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index 46469d9..1b42162 100644
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