Merge branch 'master' of github.com:id101010/vhdl-yasg

controller.vhd

@@ -1,46 +1,27 @@
 ----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    18:47:36 05/23/2016 
--- Design Name: 
--- Module Name:    controller - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 use IEEE.NUMERIC_STD.ALL;
 
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity controller is
-    Port ( clk : in  STD_LOGIC;
-			  rst: in STD_LOGIC;
-           enc_right : in  STD_LOGIC;
-           enc_ce : in  STD_LOGIC;
-			  enc_btn: in STD_LOGIC;
-			  form : in unsigned(1 downto 0);
-			  lcd_busy: in STD_LOGIC;
-			  lcd_data: out unsigned(7 downto 0);
-			  lcd_newchar: out STD_LOGIC;
-			  lcd_newpos : out STD_LOGIC;
-           freq_out : out  unsigned (16 downto 0));
+    Port ( clk : in  STD_LOGIC;                      -- Clock Input
+           rst: in STD_LOGIC;                        -- High active, async reset
+           enc_right : in  STD_LOGIC;                -- Encoder Input: 1= Direction Right, 0 = Direction Left
+           enc_ce : in  STD_LOGIC;                   -- Encoder Input: Clock Enable for Signal above
+           enc_btn: in STD_LOGIC;                    -- Encoder Input: Debounced Button (High active)
+           form : in unsigned(1 downto 0);           -- Form selection (mapping see dds.vhd)
+           lcd_busy: in STD_LOGIC;                   -- LCD Feedback: Busy Signal: 1= LCD is currently busy
+           lcd_data: out unsigned(7 downto 0);       -- LCD Output: Data output
+           lcd_newchar: out STD_LOGIC;               -- LCD Output: Send a new character to the lcd
+           lcd_newpos : out STD_LOGIC;               -- LCD Output: Send a new position/adress to the lcd
+           freq_out : out  unsigned (16 downto 0));  -- Frequency Ouput (Treshould in Hz)
 end controller;
 
 architecture Behavioral of controller is

controller_tb.vhd

@@ -1,35 +1,13 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    20:08:51 06/06/2016
--- Design Name:   
--- Module Name:   /home/timo/workspace/vhdl-yasg/controller_tb.vhd
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: controller
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
 --------------------------------------------------------------------------------
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
  
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 USE ieee.numeric_std.ALL;
  
 ENTITY controller_tb IS

dds.vhd

@@ -1,22 +1,11 @@
 ----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    11:09:53 05/16/2016 
--- Design Name: 
--- Module Name:    dds - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
@@ -24,15 +13,15 @@ use IEEE.MATH_REAL.ALL;
 use work.helpers.all;
 
 entity dds is
-    Generic (clk_freq: natural:= 50000000;
+    Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz
              freq_res: natural:=17;        -- width of frequency input (log2(max_freq))
              adc_res: natural:=12;         -- width of the ouput signal (=adc resolution)
              acc_res: natural:=32;         -- width of the phase accumulator
              phase_res: natural:=10);      -- effective phase resolution for sin lookup table
-    Port ( clk : in  STD_LOGIC;
-           freq : in  unsigned (freq_res-1 downto 0);
-           form : in  unsigned (1 downto 0);
-           amp : out  unsigned (adc_res-1 downto 0));
+    Port ( clk : in  STD_LOGIC;                        -- Clock input
+           freq : in  unsigned (freq_res-1 downto 0);  -- Frequenzy input (treshould in Hz)
+           form : in  unsigned (1 downto 0);           -- Form selection (00=Rectancle, 01=Sawtooth, 10=Triangle, 11=Sine)
+           amp : out  unsigned (adc_res-1 downto 0));  -- Signal Output (Amplitude)
 end dds;
 
 architecture Behavioral of dds is   

dds_tb.vhd

@@ -1,30 +1,11 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    11:35:57 05/16/2016
--- Design Name:   
--- Module Name:   /home/timo/vhdl-yasg/dds_tb.vhd
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: dds
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
 --------------------------------------------------------------------------------
+
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.numeric_std.ALL;

helpers.vhd

@@ -1,3 +1,10 @@
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:          GPL v3
+-- Create Date:    12:59:01 05/16/2016 
+----------------------------------------------------------------------------------
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -6,11 +13,9 @@ use IEEE.NUMERIC_STD.ALL;
 package helpers is
     --helper function to calculate the log2 (truncated) of a integer
     function log2_int(n:natural) return natural; 
-    function divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
 end helpers;
 
 
-
 package body helpers is
     function log2_int(n:natural) return natural is
         begin
@@ -19,28 +24,5 @@ package body helpers is
           end if;
           return 1; --since we can no longer divide n, return 1
     end log2_int;
-    
-    --Source: http://vhdlguru.blogspot.ch/2010/03/vhdl-function-for-division-two-signed.html
-    function  divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
-    variable a1 : unsigned(a'length-1 downto 0):=a;
-    variable b1 : unsigned(b'length-1 downto 0):=b;
-    variable p1 : unsigned(b'length downto 0):= (others => '0');
-    variable i : integer:=0;
-
-    begin
-        for i in 0 to b'length-1 loop
-            p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
-            p1(0) := a1(a'length-1);
-            a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
-            p1 := p1-b1;
-            if(p1(b'length-1) ='1') then
-                a1(0) :='0';
-                p1 := p1+b1;
-            else
-                a1(0) :='1';
-            end if;
-        end loop;
-        return a1;
-    end divide;
 end helpers;
 

io.ucf

@@ -1,3 +1,11 @@
+#---------------------------------------------------------------------------------
+#- Project:        YASG (Yet another signal generator)
+#- Project Page:   https://github.com/id101010/vhdl-yasg/
+#- Authors:        Aaron Schmocker & Timo Lang
+#- License:		    GPL v3
+#- Create Date:    16:23:12 05/20/2016 
+#---------------------------------------------------------------------------------
+
 NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
 NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
 

iseconfig/filter.filter

@@ -6,8 +6,8 @@
 <filters xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation='filter.xsd'>
 <filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_8</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
 <filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_6</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
-<filter task="xst" file="Xst" num="643" type="warning"><arg index="1" match_type="wildcard">/home/timo/workspace/vhdl-yasg/controller.vhd</arg><arg index="2" match_type="wildcard">169</arg><arg index="3" match_type="wildcard">*</arg><arg index="4" match_type="wildcard">*</arg><arg index="5" match_type="wildcard">17</arg></filter>
+<filter task="xst" file="Xst" num="643" type="warning"><arg index="1">/home/timo/workspace/vhdl-yasg/controller.vhd</arg><arg index="2" match_type="wildcard">*</arg><arg index="3" match_type="wildcard">*</arg><arg index="4" match_type="wildcard">*</arg><arg index="5">17</arg></filter>
 <filter task="xst" file="Xst" num="1896" type="warning"><arg index="1">ret_state_7</arg><arg index="2">0</arg><arg index="3">lcd_driver</arg></filter>
-<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_reg_0</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
+<filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">ret_state_reg_0</arg><arg index="2" match_type="wildcard">*</arg><arg index="3">controller</arg></filter>
 <filter task="xst" file="Xst" num="1293" type="warning"><arg index="1">lcd_data_reg_7</arg><arg index="2">0</arg><arg index="3">controller</arg></filter>
 </filters>

lcd_driver.vhd

@@ -1,45 +1,15 @@
 ----------------------------------------------------------------------------------
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
-----------------------------------------------------------------------------------
--- Company:         Berner Fachhochschule
--- Engineer:        Aaron Schmocker
--- 
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    19:29:54 05/09/2016 
--- Design Name: 
--- Module Name:     lcddriver - Behavioral 
--- Project Name:    yasg
--- Target Devices:  Spartan-3am Board
--- Tool versions: 
--- Description:     This file is part of the yasg project
---
--- Dependencies: 
---
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
 
 entity lcd_driver is
     generic (   NBITS           : natural := 21;        -- counter bit size
@@ -48,15 +18,15 @@ entity lcd_driver is
                 wait_between    : natural := 37;        -- wait 37us
                 wait_pause      : natural := 1520);     -- wait 1.52ms
                 
-    Port (  clk : in STD_LOGIC;                         -- Systemclock (50MHz)
-            reset : in STD_LOGIC;                       -- Initialize display controller
-            data : in  STD_LOGIC_VECTOR (7 downto 0);   -- either one ascii char (8bit) or new cursor position (0-31)
+    Port (  clk : in STD_LOGIC;                         -- Clock Input
+            reset : in STD_LOGIC;                       -- High active, async reset
+            data : in  STD_LOGIC_VECTOR (7 downto 0);   -- either one ascii char (8bit) or new cursor position/adress
             new_character : in  STD_LOGIC;              -- a new character is available on the data bus
             new_pos : in  STD_LOGIC;                    -- a new cursor position is available on the data bus
-            busy : out STD_LOGIC;                       -- 1 when sending stuff
-            lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd databus
-            lcd_en : out STD_LOGIC;                     -- lcd enable
-            lcd_rs : out STD_LOGIC);                    -- lcd register select
+            busy : out STD_LOGIC;                       -- output which signals that the driver/lcd is currently busy
+            lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd output: databus
+            lcd_en : out STD_LOGIC;                     -- lcd output: enable
+            lcd_rs : out STD_LOGIC);                    -- lcd output: register select
 end lcd_driver;
 
 architecture Behavioral of lcd_driver is

lcd_driver_tb.vhd

@@ -1,37 +1,14 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    21:11:41 05/16/2016
--- Design Name:   
--- Module Name:   /home/aaron/Dokumente/STUDIUM/SEM6/EloSys/EloSysDigital/Projekt/vhdl-yasg/lcd_driver_tb.vhd
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: lcd_driver
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
  
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
 ENTITY lcd_driver_tb IS
 END lcd_driver_tb;
  

rotary.vhd

@@ -1,21 +1,23 @@
------------------------------------------------------------------------------
---
--- Decoder für Drehgeber
---
------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
+-- Create Date:    19:07:22 05/23/2016 
+----------------------------------------------------------------------------------
  
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
  
 entity rotary_dec is
-    Port ( clk      : in std_logic;         -- Systemtakt
-           A        : in std_logic;         -- Spur A
-           B        : in std_logic;         -- Spur B
+    Port ( clk      : in std_logic;         -- Clock Input
+           A        : in std_logic;         -- Signal A
+           B        : in std_logic;         -- Signal B
            btn        : in std_logic;       -- Button Input
-			  btn_deb  : out std_logic;        -- Button entprellt
-           enc_right: out std_logic;        -- Zaehlrichtung
-           enc_ce   : out std_logic);        -- Clock Enable
+           btn_deb  : out std_logic;        -- Button Output Debonced
+           enc_right: out std_logic;        -- Direction Output: 1=right
+           enc_ce   : out std_logic);       -- Clock Enable Output for signal above
 
 end rotary_dec;
  

spi_driver.vhd

@@ -1,40 +1,24 @@
 ----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    12:51:31 05/17/2016 
--- Design Name: 
--- Module Name:    spi_driver - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
 ----------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
 entity spi_driver is
-	Generic (clk_freq: natural:= 50000000;
-             adc_res: natural:=12);
-    Port ( clk : in  STD_LOGIC;
-			  rst: in STD_LOGIC;
-           val : in  unsigned (adc_res-1 downto 0);
-           sck : out  STD_LOGIC;
-           cs : out  STD_LOGIC;
-           mosi : out  STD_LOGIC);
+   Generic (clk_freq: natural:= 50000000;           -- Clock-Frequency in Hz
+            adc_res: natural:=12);                  -- Number of bits the DAC has
+    Port ( clk : in  STD_LOGIC;                     -- Clock input
+           rst: in STD_LOGIC;                       -- High active, async reset
+           val : in  unsigned (adc_res-1 downto 0); -- DAC Value to write out 
+           sck : out  STD_LOGIC;                    -- SPI SCK Signal (Clock)
+           cs : out  STD_LOGIC;                     -- SPI CS Signal (Chip Select)
+           mosi : out  STD_LOGIC);                  -- SPI MOSI Signal (Master Out Slave in)
 end spi_driver;
 
 architecture Behavioral of spi_driver is

spi_driver_tb.vhd

@@ -1,35 +1,13 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
+----------------------------------------------------------------------------------
+-- Project:        YASG (Yet another signal generator)
+-- Project Page:   https://github.com/id101010/vhdl-yasg/
+-- Authors:        Aaron Schmocker & Timo Lang
+-- License:        GPL v3
 -- Create Date:    15:38:41 05/17/2016
--- Design Name:   
--- Module Name:   /home/timo/vhdl-yasg/spi_driver_tb.vhd
--- Project Name:  yasg
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: spi_driver
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
+----------------------------------------------------------------------------------
+
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
 USE ieee.numeric_std.ALL;
  
 ENTITY spi_driver_tb IS