438 lines
51 KiB
HTML
438 lines
51 KiB
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<a href="#define-members">Macros</a> |
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<a href="#func-members">Functions</a> </div>
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<div class="title">stm32f4xx_sdio.c File Reference</div> </div>
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<p>This file provides firmware functions to manage the following functionalities of the Secure digital input/output interface (SDIO) peripheral:
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<a href="#details">More...</a></p>
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<div class="textblock"><code>#include "<a class="el" href="stm32f4xx__sdio_8h_source.html">stm32f4xx_sdio.h</a>"</code><br />
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<code>#include "<a class="el" href="stm32f4xx__rcc_8h_source.html">stm32f4xx_rcc.h</a>"</code><br />
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Include dependency graph for stm32f4xx_sdio.c:</div>
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</div><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:gabf07aced03df5f46d57cea1d4f56d1e3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabf07aced03df5f46d57cea1d4f56d1e3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDIO_OFFSET</b>   (SDIO_BASE - <a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a>)</td></tr>
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<tr class="separator:gabf07aced03df5f46d57cea1d4f56d1e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac5d642be874338519fdec175204ca8ed"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac5d642be874338519fdec175204ca8ed"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CLKCR_OFFSET</b>   (SDIO_OFFSET + 0x04)</td></tr>
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<tr class="separator:gac5d642be874338519fdec175204ca8ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6ad1da47f9d84c54eb620b9231ebec86"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6ad1da47f9d84c54eb620b9231ebec86"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CLKEN_BitNumber</b>   0x08</td></tr>
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<tr class="separator:ga6ad1da47f9d84c54eb620b9231ebec86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabfb5772b9b734972b576309f7ca8bf92"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabfb5772b9b734972b576309f7ca8bf92"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CLKCR_CLKEN_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))</td></tr>
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<tr class="separator:gabfb5772b9b734972b576309f7ca8bf92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf12d26702ce7a88d2a3dae87f000b75e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf12d26702ce7a88d2a3dae87f000b75e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CMD_OFFSET</b>   (SDIO_OFFSET + 0x0C)</td></tr>
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<tr class="separator:gaf12d26702ce7a88d2a3dae87f000b75e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf88f03a42d76974b55dfb8bda65ade97"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf88f03a42d76974b55dfb8bda65ade97"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDIOSUSPEND_BitNumber</b>   0x0B</td></tr>
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<tr class="separator:gaf88f03a42d76974b55dfb8bda65ade97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga931e48aa282e2a937308f57f807e0781"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga931e48aa282e2a937308f57f807e0781"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CMD_SDIOSUSPEND_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))</td></tr>
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<tr class="separator:ga931e48aa282e2a937308f57f807e0781"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1d1112c7b804791a0fffd8b317085aeb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1d1112c7b804791a0fffd8b317085aeb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>ENCMDCOMPL_BitNumber</b>   0x0C</td></tr>
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<tr class="separator:ga1d1112c7b804791a0fffd8b317085aeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gade06098d1616639ce5f1b70675280b7c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gade06098d1616639ce5f1b70675280b7c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CMD_ENCMDCOMPL_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))</td></tr>
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<tr class="separator:gade06098d1616639ce5f1b70675280b7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab6d83a7ccd4a0d9ea9a09fec263fb25f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab6d83a7ccd4a0d9ea9a09fec263fb25f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>NIEN_BitNumber</b>   0x0D</td></tr>
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<tr class="separator:gab6d83a7ccd4a0d9ea9a09fec263fb25f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga08623f1d053677de8b20a6f5f5090edd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga08623f1d053677de8b20a6f5f5090edd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CMD_NIEN_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))</td></tr>
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<tr class="separator:ga08623f1d053677de8b20a6f5f5090edd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd4fd3bb700b879f843ccc867db1832e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabd4fd3bb700b879f843ccc867db1832e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>ATACMD_BitNumber</b>   0x0E</td></tr>
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<tr class="separator:gabd4fd3bb700b879f843ccc867db1832e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabb7e537f931b6fdd3b49e826f2e19d7c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb7e537f931b6fdd3b49e826f2e19d7c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CMD_ATACMD_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))</td></tr>
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<tr class="separator:gabb7e537f931b6fdd3b49e826f2e19d7c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga948c1382c4cfd3af3e406c4d0cdd4240"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga948c1382c4cfd3af3e406c4d0cdd4240"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DCTRL_OFFSET</b>   (SDIO_OFFSET + 0x2C)</td></tr>
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<tr class="separator:ga948c1382c4cfd3af3e406c4d0cdd4240"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab2af311e327213503f0dbf3d013b7944"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab2af311e327213503f0dbf3d013b7944"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DMAEN_BitNumber</b>   0x03</td></tr>
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<tr class="separator:gab2af311e327213503f0dbf3d013b7944"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga43f7336d4f955c6cf1f676ccbc043fe9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga43f7336d4f955c6cf1f676ccbc043fe9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DCTRL_DMAEN_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))</td></tr>
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<tr class="separator:ga43f7336d4f955c6cf1f676ccbc043fe9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga773045c51d3e8daee0c181517c44a2df"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga773045c51d3e8daee0c181517c44a2df"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RWSTART_BitNumber</b>   0x08</td></tr>
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<tr class="separator:ga773045c51d3e8daee0c181517c44a2df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac776c39dfac0e1ed007217133e1145c3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac776c39dfac0e1ed007217133e1145c3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DCTRL_RWSTART_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>RWSTOP_BitNumber</b>   0x09</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DCTRL_RWSTOP_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>RWMOD_BitNumber</b>   0x0A</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DCTRL_RWMOD_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))</td></tr>
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<tr class="memitem:ga37f3e1612e0dae8160be978ebfa54301"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga37f3e1612e0dae8160be978ebfa54301"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDIOEN_BitNumber</b>   0x0B</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DCTRL_SDIOEN_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))</td></tr>
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<tr class="memitem:gac8d10dd1e49ca9e8a6954146654e9a01"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac8d10dd1e49ca9e8a6954146654e9a01"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CLKCR_CLEAR_MASK</b>   ((uint32_t)0xFFFF8100)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>PWR_PWRCTRL_MASK</b>   ((uint32_t)0xFFFFFFFC)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>DCTRL_CLEAR_MASK</b>   ((uint32_t)0xFFFFFF08)</td></tr>
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<tr class="memitem:ga2325d77090e44221b07f8fba5bc9217e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2325d77090e44221b07f8fba5bc9217e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CMD_CLEAR_MASK</b>   ((uint32_t)0xFFFFF800)</td></tr>
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<tr class="memitem:ga4285ce49b005e3d03ddf9fdc491c4d70"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4285ce49b005e3d03ddf9fdc491c4d70"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDIO_RESP_ADDR</b>   ((uint32_t)(SDIO_BASE + 0x14))</td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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Functions</h2></td></tr>
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<tr class="memitem:gac359d2c6c67a2590f8f9b720c0e4ff1b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group1.html#gac359d2c6c67a2590f8f9b720c0e4ff1b">SDIO_DeInit</a> (void)</td></tr>
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<tr class="memdesc:gac359d2c6c67a2590f8f9b720c0e4ff1b"><td class="mdescLeft"> </td><td class="mdescRight">Deinitializes the SDIO peripheral registers to their default reset values. <a href="group___s_d_i_o___group1.html#gac359d2c6c67a2590f8f9b720c0e4ff1b">More...</a><br /></td></tr>
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<tr class="separator:gac359d2c6c67a2590f8f9b720c0e4ff1b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad40764a8e37c0ed5c9141ae338ff0203"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group1.html#gad40764a8e37c0ed5c9141ae338ff0203">SDIO_Init</a> (<a class="el" href="struct_s_d_i_o___init_type_def.html">SDIO_InitTypeDef</a> *SDIO_InitStruct)</td></tr>
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<tr class="memdesc:gad40764a8e37c0ed5c9141ae338ff0203"><td class="mdescLeft"> </td><td class="mdescRight">Initializes the SDIO peripheral according to the specified parameters in the SDIO_InitStruct. <a href="group___s_d_i_o___group1.html#gad40764a8e37c0ed5c9141ae338ff0203">More...</a><br /></td></tr>
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<tr class="separator:gad40764a8e37c0ed5c9141ae338ff0203"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga778d338c29df4fae9ef69432e6df32ad"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group1.html#ga778d338c29df4fae9ef69432e6df32ad">SDIO_StructInit</a> (<a class="el" href="struct_s_d_i_o___init_type_def.html">SDIO_InitTypeDef</a> *SDIO_InitStruct)</td></tr>
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<tr class="memdesc:ga778d338c29df4fae9ef69432e6df32ad"><td class="mdescLeft"> </td><td class="mdescRight">Fills each SDIO_InitStruct member with its default value. <a href="group___s_d_i_o___group1.html#ga778d338c29df4fae9ef69432e6df32ad">More...</a><br /></td></tr>
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<tr class="separator:ga778d338c29df4fae9ef69432e6df32ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7243b857d6b323748ff3a493b265bedc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group1.html#ga7243b857d6b323748ff3a493b265bedc">SDIO_ClockCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga7243b857d6b323748ff3a493b265bedc"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the SDIO Clock. <a href="group___s_d_i_o___group1.html#ga7243b857d6b323748ff3a493b265bedc">More...</a><br /></td></tr>
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<tr class="separator:ga7243b857d6b323748ff3a493b265bedc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga36ecca32b904de74218fbe65cd5f5270"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group1.html#ga36ecca32b904de74218fbe65cd5f5270">SDIO_SetPowerState</a> (uint32_t SDIO_PowerState)</td></tr>
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<tr class="memdesc:ga36ecca32b904de74218fbe65cd5f5270"><td class="mdescLeft"> </td><td class="mdescRight">Sets the power status of the controller. <a href="group___s_d_i_o___group1.html#ga36ecca32b904de74218fbe65cd5f5270">More...</a><br /></td></tr>
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<tr class="separator:ga36ecca32b904de74218fbe65cd5f5270"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3a19de2c7cd51645702213f64a1758ed"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group1.html#ga3a19de2c7cd51645702213f64a1758ed">SDIO_GetPowerState</a> (void)</td></tr>
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<tr class="memdesc:ga3a19de2c7cd51645702213f64a1758ed"><td class="mdescLeft"> </td><td class="mdescRight">Gets the power status of the controller. <a href="group___s_d_i_o___group1.html#ga3a19de2c7cd51645702213f64a1758ed">More...</a><br /></td></tr>
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<tr class="separator:ga3a19de2c7cd51645702213f64a1758ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7117d2f702703f6c0a66bc07707cab23"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group2.html#ga7117d2f702703f6c0a66bc07707cab23">SDIO_SendCommand</a> (<a class="el" href="struct_s_d_i_o___cmd_init_type_def.html">SDIO_CmdInitTypeDef</a> *SDIO_CmdInitStruct)</td></tr>
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<tr class="memdesc:ga7117d2f702703f6c0a66bc07707cab23"><td class="mdescLeft"> </td><td class="mdescRight">Initializes the SDIO Command according to the specified parameters in the SDIO_CmdInitStruct and send the command. <a href="group___s_d_i_o___group2.html#ga7117d2f702703f6c0a66bc07707cab23">More...</a><br /></td></tr>
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<tr class="separator:ga7117d2f702703f6c0a66bc07707cab23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09d9e89f49c87c82aec79c97b7068e24"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group2.html#ga09d9e89f49c87c82aec79c97b7068e24">SDIO_CmdStructInit</a> (<a class="el" href="struct_s_d_i_o___cmd_init_type_def.html">SDIO_CmdInitTypeDef</a> *SDIO_CmdInitStruct)</td></tr>
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<tr class="memdesc:ga09d9e89f49c87c82aec79c97b7068e24"><td class="mdescLeft"> </td><td class="mdescRight">Fills each SDIO_CmdInitStruct member with its default value. <a href="group___s_d_i_o___group2.html#ga09d9e89f49c87c82aec79c97b7068e24">More...</a><br /></td></tr>
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<tr class="separator:ga09d9e89f49c87c82aec79c97b7068e24"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9badf271c818e09da301d715c4ad0e5b"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group2.html#ga9badf271c818e09da301d715c4ad0e5b">SDIO_GetCommandResponse</a> (void)</td></tr>
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<tr class="memdesc:ga9badf271c818e09da301d715c4ad0e5b"><td class="mdescLeft"> </td><td class="mdescRight">Returns command index of last command for which response received. <a href="group___s_d_i_o___group2.html#ga9badf271c818e09da301d715c4ad0e5b">More...</a><br /></td></tr>
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<tr class="separator:ga9badf271c818e09da301d715c4ad0e5b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5c1e859511840e8cca6a9a768bce220b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group2.html#ga5c1e859511840e8cca6a9a768bce220b">SDIO_GetResponse</a> (uint32_t SDIO_RESP)</td></tr>
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<tr class="memdesc:ga5c1e859511840e8cca6a9a768bce220b"><td class="mdescLeft"> </td><td class="mdescRight">Returns response received from the card for the last command. <a href="group___s_d_i_o___group2.html#ga5c1e859511840e8cca6a9a768bce220b">More...</a><br /></td></tr>
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<tr class="separator:ga5c1e859511840e8cca6a9a768bce220b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad65d896ae919683585bda44a1e2afae4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group3.html#gad65d896ae919683585bda44a1e2afae4">SDIO_DataConfig</a> (<a class="el" href="struct_s_d_i_o___data_init_type_def.html">SDIO_DataInitTypeDef</a> *SDIO_DataInitStruct)</td></tr>
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<tr class="memdesc:gad65d896ae919683585bda44a1e2afae4"><td class="mdescLeft"> </td><td class="mdescRight">Initializes the SDIO data path according to the specified parameters in the SDIO_DataInitStruct. <a href="group___s_d_i_o___group3.html#gad65d896ae919683585bda44a1e2afae4">More...</a><br /></td></tr>
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<tr class="separator:gad65d896ae919683585bda44a1e2afae4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa83209c09e921521aca2587fb5b22ea2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group3.html#gaa83209c09e921521aca2587fb5b22ea2">SDIO_DataStructInit</a> (<a class="el" href="struct_s_d_i_o___data_init_type_def.html">SDIO_DataInitTypeDef</a> *SDIO_DataInitStruct)</td></tr>
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<tr class="memdesc:gaa83209c09e921521aca2587fb5b22ea2"><td class="mdescLeft"> </td><td class="mdescRight">Fills each SDIO_DataInitStruct member with its default value. <a href="group___s_d_i_o___group3.html#gaa83209c09e921521aca2587fb5b22ea2">More...</a><br /></td></tr>
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<tr class="separator:gaa83209c09e921521aca2587fb5b22ea2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7a28aaa2c25a9a5a8db1f49b0e8c9d0a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group3.html#ga7a28aaa2c25a9a5a8db1f49b0e8c9d0a">SDIO_GetDataCounter</a> (void)</td></tr>
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<tr class="memdesc:ga7a28aaa2c25a9a5a8db1f49b0e8c9d0a"><td class="mdescLeft"> </td><td class="mdescRight">Returns number of remaining data bytes to be transferred. <a href="group___s_d_i_o___group3.html#ga7a28aaa2c25a9a5a8db1f49b0e8c9d0a">More...</a><br /></td></tr>
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<tr class="separator:ga7a28aaa2c25a9a5a8db1f49b0e8c9d0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e8ac755ef3c31ecd4ed2708df19187e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group3.html#ga4e8ac755ef3c31ecd4ed2708df19187e">SDIO_ReadData</a> (void)</td></tr>
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<tr class="memdesc:ga4e8ac755ef3c31ecd4ed2708df19187e"><td class="mdescLeft"> </td><td class="mdescRight">Read one data word from Rx FIFO. <a href="group___s_d_i_o___group3.html#ga4e8ac755ef3c31ecd4ed2708df19187e">More...</a><br /></td></tr>
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<tr class="separator:ga4e8ac755ef3c31ecd4ed2708df19187e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga361008b5252aa33b5f2b5823ee3d7240"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group3.html#ga361008b5252aa33b5f2b5823ee3d7240">SDIO_WriteData</a> (uint32_t Data)</td></tr>
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<tr class="memdesc:ga361008b5252aa33b5f2b5823ee3d7240"><td class="mdescLeft"> </td><td class="mdescRight">Write one data word to Tx FIFO. <a href="group___s_d_i_o___group3.html#ga361008b5252aa33b5f2b5823ee3d7240">More...</a><br /></td></tr>
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<tr class="separator:ga361008b5252aa33b5f2b5823ee3d7240"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9a3343983a2d68b5164a1c89797d2dd6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group3.html#ga9a3343983a2d68b5164a1c89797d2dd6">SDIO_GetFIFOCount</a> (void)</td></tr>
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<tr class="memdesc:ga9a3343983a2d68b5164a1c89797d2dd6"><td class="mdescLeft"> </td><td class="mdescRight">Returns the number of words left to be written to or read from FIFO. <a href="group___s_d_i_o___group3.html#ga9a3343983a2d68b5164a1c89797d2dd6">More...</a><br /></td></tr>
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<tr class="separator:ga9a3343983a2d68b5164a1c89797d2dd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac88f914d9a68a83abc2265ec8a7b79fc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group4.html#gac88f914d9a68a83abc2265ec8a7b79fc">SDIO_StartSDIOReadWait</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:gac88f914d9a68a83abc2265ec8a7b79fc"><td class="mdescLeft"> </td><td class="mdescRight">Starts the SD I/O Read Wait operation. <a href="group___s_d_i_o___group4.html#gac88f914d9a68a83abc2265ec8a7b79fc">More...</a><br /></td></tr>
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<tr class="separator:gac88f914d9a68a83abc2265ec8a7b79fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca6b25eb2debb73ac827c66f0ebcf837"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group4.html#gaca6b25eb2debb73ac827c66f0ebcf837">SDIO_StopSDIOReadWait</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaca6b25eb2debb73ac827c66f0ebcf837"><td class="mdescLeft"> </td><td class="mdescRight">Stops the SD I/O Read Wait operation. <a href="group___s_d_i_o___group4.html#gaca6b25eb2debb73ac827c66f0ebcf837">More...</a><br /></td></tr>
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<tr class="separator:gaca6b25eb2debb73ac827c66f0ebcf837"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2baac4ea1bb6c2d94345d2712604338a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group4.html#ga2baac4ea1bb6c2d94345d2712604338a">SDIO_SetSDIOReadWaitMode</a> (uint32_t SDIO_ReadWaitMode)</td></tr>
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<tr class="memdesc:ga2baac4ea1bb6c2d94345d2712604338a"><td class="mdescLeft"> </td><td class="mdescRight">Sets one of the two options of inserting read wait interval. <a href="group___s_d_i_o___group4.html#ga2baac4ea1bb6c2d94345d2712604338a">More...</a><br /></td></tr>
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<tr class="separator:ga2baac4ea1bb6c2d94345d2712604338a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga24e210c185d5a7855cbaff4472a8f8d1"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group4.html#ga24e210c185d5a7855cbaff4472a8f8d1">SDIO_SetSDIOOperation</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga24e210c185d5a7855cbaff4472a8f8d1"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the SD I/O Mode Operation. <a href="group___s_d_i_o___group4.html#ga24e210c185d5a7855cbaff4472a8f8d1">More...</a><br /></td></tr>
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<tr class="separator:ga24e210c185d5a7855cbaff4472a8f8d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9264137a01a1ab81d03bc80a3b3120fc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group4.html#ga9264137a01a1ab81d03bc80a3b3120fc">SDIO_SendSDIOSuspendCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga9264137a01a1ab81d03bc80a3b3120fc"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the SD I/O Mode suspend command sending. <a href="group___s_d_i_o___group4.html#ga9264137a01a1ab81d03bc80a3b3120fc">More...</a><br /></td></tr>
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<tr class="separator:ga9264137a01a1ab81d03bc80a3b3120fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1bbe98c629812bc62121d9c8b2c5e21b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group5.html#ga1bbe98c629812bc62121d9c8b2c5e21b">SDIO_CommandCompletionCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga1bbe98c629812bc62121d9c8b2c5e21b"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the command completion signal. <a href="group___s_d_i_o___group5.html#ga1bbe98c629812bc62121d9c8b2c5e21b">More...</a><br /></td></tr>
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<tr class="separator:ga1bbe98c629812bc62121d9c8b2c5e21b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab44b8cbc21be000a291563076159503b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group5.html#gab44b8cbc21be000a291563076159503b">SDIO_CEATAITCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:gab44b8cbc21be000a291563076159503b"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the CE-ATA interrupt. <a href="group___s_d_i_o___group5.html#gab44b8cbc21be000a291563076159503b">More...</a><br /></td></tr>
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<tr class="separator:gab44b8cbc21be000a291563076159503b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8dc7f17804bdb745b42f6647c8487b4c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group5.html#ga8dc7f17804bdb745b42f6647c8487b4c">SDIO_SendCEATACmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga8dc7f17804bdb745b42f6647c8487b4c"><td class="mdescLeft"> </td><td class="mdescRight">Sends CE-ATA command (CMD61). <a href="group___s_d_i_o___group5.html#ga8dc7f17804bdb745b42f6647c8487b4c">More...</a><br /></td></tr>
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<tr class="separator:ga8dc7f17804bdb745b42f6647c8487b4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad36fde5ec0ce0c2089b9d971c2271e6e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group6.html#gad36fde5ec0ce0c2089b9d971c2271e6e">SDIO_DMACmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:gad36fde5ec0ce0c2089b9d971c2271e6e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the SDIO DMA request. <a href="group___s_d_i_o___group6.html#gad36fde5ec0ce0c2089b9d971c2271e6e">More...</a><br /></td></tr>
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<tr class="separator:gad36fde5ec0ce0c2089b9d971c2271e6e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga208f51237ef43288735829dbaed37f00"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group7.html#ga208f51237ef43288735829dbaed37f00">SDIO_ITConfig</a> (uint32_t SDIO_IT, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga208f51237ef43288735829dbaed37f00"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the SDIO interrupts. <a href="group___s_d_i_o___group7.html#ga208f51237ef43288735829dbaed37f00">More...</a><br /></td></tr>
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<tr class="separator:ga208f51237ef43288735829dbaed37f00"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga644514b4b3c95c5c4326d99cd166f6f9"><td class="memItemLeft" align="right" valign="top">FlagStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group7.html#ga644514b4b3c95c5c4326d99cd166f6f9">SDIO_GetFlagStatus</a> (uint32_t SDIO_FLAG)</td></tr>
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<tr class="memdesc:ga644514b4b3c95c5c4326d99cd166f6f9"><td class="mdescLeft"> </td><td class="mdescRight">Checks whether the specified SDIO flag is set or not. <a href="group___s_d_i_o___group7.html#ga644514b4b3c95c5c4326d99cd166f6f9">More...</a><br /></td></tr>
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<tr class="separator:ga644514b4b3c95c5c4326d99cd166f6f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga7aff4efdeb528229135f9f285e53518a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group7.html#ga7aff4efdeb528229135f9f285e53518a">SDIO_ClearFlag</a> (uint32_t SDIO_FLAG)</td></tr>
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<tr class="memdesc:ga7aff4efdeb528229135f9f285e53518a"><td class="mdescLeft"> </td><td class="mdescRight">Clears the SDIO's pending flags. <a href="group___s_d_i_o___group7.html#ga7aff4efdeb528229135f9f285e53518a">More...</a><br /></td></tr>
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<tr class="separator:ga7aff4efdeb528229135f9f285e53518a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2d64af1f3df0f99cb518f9a89bbd02ac"><td class="memItemLeft" align="right" valign="top">ITStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group7.html#ga2d64af1f3df0f99cb518f9a89bbd02ac">SDIO_GetITStatus</a> (uint32_t SDIO_IT)</td></tr>
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<tr class="memdesc:ga2d64af1f3df0f99cb518f9a89bbd02ac"><td class="mdescLeft"> </td><td class="mdescRight">Checks whether the specified SDIO interrupt has occurred or not. <a href="group___s_d_i_o___group7.html#ga2d64af1f3df0f99cb518f9a89bbd02ac">More...</a><br /></td></tr>
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<tr class="separator:ga2d64af1f3df0f99cb518f9a89bbd02ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga048e07fd86321cd01b2a22c071c3149b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___s_d_i_o___group7.html#ga048e07fd86321cd01b2a22c071c3149b">SDIO_ClearITPendingBit</a> (uint32_t SDIO_IT)</td></tr>
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<tr class="memdesc:ga048e07fd86321cd01b2a22c071c3149b"><td class="mdescLeft"> </td><td class="mdescRight">Clears the SDIO's interrupt pending bits. <a href="group___s_d_i_o___group7.html#ga048e07fd86321cd01b2a22c071c3149b">More...</a><br /></td></tr>
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<tr class="separator:ga048e07fd86321cd01b2a22c071c3149b"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>This file provides firmware functions to manage the following functionalities of the Secure digital input/output interface (SDIO) peripheral: </p>
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<dl class="section author"><dt>Author</dt><dd>MCD Application Team </dd></dl>
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<dl class="section version"><dt>Version</dt><dd>V1.4.0 </dd></dl>
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<dl class="section date"><dt>Date</dt><dd>04-August-2014<ul>
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<li>Initialization and Configuration</li>
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<li>Command path state machine (CPSM) management</li>
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<li>Data path state machine (DPSM) management</li>
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<li>SDIO IO Cards mode management</li>
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<li>CE-ATA mode management</li>
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<li>DMA transfers management</li>
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<li>Interrupts and flags management</li>
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</ul>
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</dd></dl>
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<pre class="fragment"> ===================================================================
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##### How to use this driver #####
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===================================================================
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[..]
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(#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
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(PLL48CLK). Before to start working with SDIO peripheral make sure that the
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PLL is well configured.
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The SDIO peripheral uses two clock signals:
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(++) SDIO adapter clock (SDIOCLK = 48 MHz)
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(++) APB2 bus clock (PCLK2)
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-@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
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Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
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(#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
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(#) According to the SDIO mode, enable the GPIO clocks using
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RCC_AHB1PeriphClockCmd() function.
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The I/O can be one of the following configurations:
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(++) 1-bit data length: SDIO_CMD, SDIO_CK and D0.
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(++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
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(++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].
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(#) Peripheral alternate function:
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(++) Connect the pin to the desired peripherals' Alternate Function (AF)
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using GPIO_PinAFConfig() function
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(++) Configure the desired pin in alternate function by:
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GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
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(++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd,
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GPIO_OType and GPIO_Speed members
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(++) Call GPIO_Init() function
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(#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
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hardware, flow control and the Clock Divider using the SDIO_Init()
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function.
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(#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
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function.
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(#) Enable the clock using the SDIO_ClockCmd() function.
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(#) Enable the NVIC and the corresponding interrupt using the function
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SDIO_ITConfig() if you need to use interrupt mode.
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(#) When using the DMA mode
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(++) Configure the DMA using DMA_Init() function
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(++) Active the needed channel Request using SDIO_DMACmd() function
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(#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
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(#) To control the CPSM (Command Path State Machine) and send
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commands to the card use the SDIO_SendCommand(),
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SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
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to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
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to the selected command to be sent.
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The parameters that should be filled are:
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(++) Command Argument
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(++) Command Index
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(++) Command Response type
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(++) Command Wait
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(++) CPSM Status (Enable or Disable).
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|
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-@@- To check if the command is well received, read the SDIO_CMDRESP
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register using the SDIO_GetCommandResponse().
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The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
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SDIO_GetResponse() function.
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(#) To control the DPSM (Data Path State Machine) and send/receive
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data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
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SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
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*** Read Operations ***
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=======================
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[..]
|
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(#) First, user has to fill the data structure (pointer to
|
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SDIO_DataInitTypeDef) according to the selected data type to be received.
|
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The parameters that should be filled are:
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(++) Data TimeOut
|
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(++) Data Length
|
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(++) Data Block size
|
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(++) Data Transfer direction: should be from card (To SDIO)
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(++) Data Transfer mode
|
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(++) DPSM Status (Enable or Disable)
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|
|
|
(#) Configure the SDIO resources to receive the data from the card
|
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according to selected transfer mode (Refer to Step 8, 9 and 10).
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|
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(#) Send the selected Read command (refer to step 11).
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|
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(#) Use the SDIO flags/interrupts to check the transfer status.
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|
|
*** Write Operations ***
|
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========================
|
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[..]
|
|
(#) First, user has to fill the data structure (pointer to
|
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SDIO_DataInitTypeDef) according to the selected data type to be received.
|
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The parameters that should be filled are:
|
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(++) Data TimeOut
|
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(++) Data Length
|
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(++) Data Block size
|
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(++) Data Transfer direction: should be to card (To CARD)
|
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(++) Data Transfer mode
|
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(++) DPSM Status (Enable or Disable)
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|
|
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(#) Configure the SDIO resources to send the data to the card according to
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selected transfer mode (Refer to Step 8, 9 and 10).
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(#) Send the selected Write command (refer to step 11).
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|
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(#) Use the SDIO flags/interrupts to check the transfer status.</pre><pre class="fragment">@attention
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<h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
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|
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Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
|
You may not use this file except in compliance with the License.
|
|
You may obtain a copy of the License at:
|
|
|
|
http://www.st.com/software_license_agreement_liberty_v2
|
|
|
|
Unless required by applicable law or agreed to in writing, software
|
|
distributed under the License is distributed on an "AS IS" BASIS,
|
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
See the License for the specific language governing permissions and
|
|
limitations under the License.</pre></div></div><!-- contents -->
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