1535 lines
80 KiB
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1535 lines
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<a href="#func-members">Functions</a> </div>
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<div class="title">Peripheral clocks configuration functions<div class="ingroups"><a class="el" href="group___s_t_m32_f4xx___std_periph___driver.html">STM32F4xx_StdPeriph_Driver</a> » <a class="el" href="group___r_c_c.html">RCC</a> » <a class="el" href="group___r_c_c___private___functions.html">RCC_Private_Functions</a></div></div> </div>
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<p>Peripheral clocks configuration functions.
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Collaboration diagram for Peripheral clocks configuration functions:</div>
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<center><table><tr><td><img src="group___r_c_c___group3.png" border="0" alt="" usemap="#group______r__c__c______group3"/>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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Functions</h2></td></tr>
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<tr class="memitem:ga1473d8a5a020642966359611c44181b0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga1473d8a5a020642966359611c44181b0">RCC_RTCCLKConfig</a> (uint32_t RCC_RTCCLKSource)</td></tr>
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<tr class="memdesc:ga1473d8a5a020642966359611c44181b0"><td class="mdescLeft"> </td><td class="mdescRight">Configures the RTC clock (RTCCLK). <a href="#ga1473d8a5a020642966359611c44181b0">More...</a><br /></td></tr>
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<tr class="separator:ga1473d8a5a020642966359611c44181b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9802f84846df2cea8e369234ed13b159"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga9802f84846df2cea8e369234ed13b159">RCC_RTCCLKCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga9802f84846df2cea8e369234ed13b159"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the RTC clock. <a href="#ga9802f84846df2cea8e369234ed13b159">More...</a><br /></td></tr>
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<tr class="separator:ga9802f84846df2cea8e369234ed13b159"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga636c3b72f35391e67f12a551b15fa54a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga636c3b72f35391e67f12a551b15fa54a">RCC_BackupResetCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga636c3b72f35391e67f12a551b15fa54a"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases the Backup domain reset. <a href="#ga636c3b72f35391e67f12a551b15fa54a">More...</a><br /></td></tr>
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<tr class="separator:ga636c3b72f35391e67f12a551b15fa54a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c56f8529988fcc8f4dbffbc1bab27d0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga6c56f8529988fcc8f4dbffbc1bab27d0">RCC_I2SCLKConfig</a> (uint32_t RCC_I2SCLKSource)</td></tr>
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<tr class="memdesc:ga6c56f8529988fcc8f4dbffbc1bab27d0"><td class="mdescLeft"> </td><td class="mdescRight">Configures the I2S clock source (I2SCLK). <a href="#ga6c56f8529988fcc8f4dbffbc1bab27d0">More...</a><br /></td></tr>
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<tr class="separator:ga6c56f8529988fcc8f4dbffbc1bab27d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71a887e0e7ef3d49ff87f2cbc435b099"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga71a887e0e7ef3d49ff87f2cbc435b099">RCC_SAIPLLI2SClkDivConfig</a> (uint32_t RCC_PLLI2SDivQ)</td></tr>
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<tr class="memdesc:ga71a887e0e7ef3d49ff87f2cbc435b099"><td class="mdescLeft"> </td><td class="mdescRight">Configures the SAI clock Divider coming from PLLI2S. <a href="#ga71a887e0e7ef3d49ff87f2cbc435b099">More...</a><br /></td></tr>
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<tr class="separator:ga71a887e0e7ef3d49ff87f2cbc435b099"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabefc354915bd57804329349ec3f33fab"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gabefc354915bd57804329349ec3f33fab">RCC_SAIPLLSAIClkDivConfig</a> (uint32_t RCC_PLLSAIDivQ)</td></tr>
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<tr class="memdesc:gabefc354915bd57804329349ec3f33fab"><td class="mdescLeft"> </td><td class="mdescRight">Configures the SAI clock Divider coming from PLLSAI. <a href="#gabefc354915bd57804329349ec3f33fab">More...</a><br /></td></tr>
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<tr class="separator:gabefc354915bd57804329349ec3f33fab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cb4739d834adbf4009112357e1b1099"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga6cb4739d834adbf4009112357e1b1099">RCC_SAIBlockACLKConfig</a> (uint32_t RCC_SAIBlockACLKSource)</td></tr>
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<tr class="memdesc:ga6cb4739d834adbf4009112357e1b1099"><td class="mdescLeft"> </td><td class="mdescRight">Configures SAI1BlockA clock source selection. <a href="#ga6cb4739d834adbf4009112357e1b1099">More...</a><br /></td></tr>
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<tr class="separator:ga6cb4739d834adbf4009112357e1b1099"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d1fb5c9a743d7f36713c9c76d386557"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga4d1fb5c9a743d7f36713c9c76d386557">RCC_SAIBlockBCLKConfig</a> (uint32_t RCC_SAIBlockBCLKSource)</td></tr>
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<tr class="memdesc:ga4d1fb5c9a743d7f36713c9c76d386557"><td class="mdescLeft"> </td><td class="mdescRight">Configures SAI1BlockB clock source selection. <a href="#ga4d1fb5c9a743d7f36713c9c76d386557">More...</a><br /></td></tr>
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<tr class="separator:ga4d1fb5c9a743d7f36713c9c76d386557"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac04a91996aefd2a517cf90c2a44830d2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gac04a91996aefd2a517cf90c2a44830d2">RCC_LTDCCLKDivConfig</a> (uint32_t RCC_PLLSAIDivR)</td></tr>
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<tr class="memdesc:gac04a91996aefd2a517cf90c2a44830d2"><td class="mdescLeft"> </td><td class="mdescRight">Configures the LTDC clock Divider coming from PLLSAI. <a href="#gac04a91996aefd2a517cf90c2a44830d2">More...</a><br /></td></tr>
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<tr class="separator:gac04a91996aefd2a517cf90c2a44830d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0599100e7afdf8ed988e351a899e922"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaf0599100e7afdf8ed988e351a899e922">RCC_TIMCLKPresConfig</a> (uint32_t RCC_TIMCLKPrescaler)</td></tr>
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<tr class="memdesc:gaf0599100e7afdf8ed988e351a899e922"><td class="mdescLeft"> </td><td class="mdescRight">Configures the Timers clocks prescalers selection. <a href="#gaf0599100e7afdf8ed988e351a899e922">More...</a><br /></td></tr>
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<tr class="separator:gaf0599100e7afdf8ed988e351a899e922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80c89116820d48bb38db2e7d5e5a49b9"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga80c89116820d48bb38db2e7d5e5a49b9">RCC_AHB1PeriphClockCmd</a> (uint32_t RCC_AHB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga80c89116820d48bb38db2e7d5e5a49b9"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB1 peripheral clock. <a href="#ga80c89116820d48bb38db2e7d5e5a49b9">More...</a><br /></td></tr>
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<tr class="separator:ga80c89116820d48bb38db2e7d5e5a49b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadffedbd87e796f01d9776b8ee01ff5e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaadffedbd87e796f01d9776b8ee01ff5e">RCC_AHB2PeriphClockCmd</a> (uint32_t RCC_AHB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaadffedbd87e796f01d9776b8ee01ff5e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB2 peripheral clock. <a href="#gaadffedbd87e796f01d9776b8ee01ff5e">More...</a><br /></td></tr>
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<tr class="separator:gaadffedbd87e796f01d9776b8ee01ff5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4eb8c119f2e9bf2bd2e042d27f151338"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga4eb8c119f2e9bf2bd2e042d27f151338">RCC_AHB3PeriphClockCmd</a> (uint32_t RCC_AHB3Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga4eb8c119f2e9bf2bd2e042d27f151338"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB3 peripheral clock. <a href="#ga4eb8c119f2e9bf2bd2e042d27f151338">More...</a><br /></td></tr>
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<tr class="separator:ga4eb8c119f2e9bf2bd2e042d27f151338"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee7cc5d73af7fe1986fceff8afd3973e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaee7cc5d73af7fe1986fceff8afd3973e">RCC_APB1PeriphClockCmd</a> (uint32_t RCC_APB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaee7cc5d73af7fe1986fceff8afd3973e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Low Speed APB (APB1) peripheral clock. <a href="#gaee7cc5d73af7fe1986fceff8afd3973e">More...</a><br /></td></tr>
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<tr class="separator:gaee7cc5d73af7fe1986fceff8afd3973e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56ff55caf8d835351916b40dd030bc87"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga56ff55caf8d835351916b40dd030bc87">RCC_APB2PeriphClockCmd</a> (uint32_t RCC_APB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga56ff55caf8d835351916b40dd030bc87"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the High Speed APB (APB2) peripheral clock. <a href="#ga56ff55caf8d835351916b40dd030bc87">More...</a><br /></td></tr>
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<tr class="separator:ga56ff55caf8d835351916b40dd030bc87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7c450567f4731d4f0615f63586cad86"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaa7c450567f4731d4f0615f63586cad86">RCC_AHB1PeriphResetCmd</a> (uint32_t RCC_AHB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaa7c450567f4731d4f0615f63586cad86"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases AHB1 peripheral reset. <a href="#gaa7c450567f4731d4f0615f63586cad86">More...</a><br /></td></tr>
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<tr class="separator:gaa7c450567f4731d4f0615f63586cad86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb119d6d1955d1b8c361e8140845ac5a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gafb119d6d1955d1b8c361e8140845ac5a">RCC_AHB2PeriphResetCmd</a> (uint32_t RCC_AHB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gafb119d6d1955d1b8c361e8140845ac5a"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases AHB2 peripheral reset. <a href="#gafb119d6d1955d1b8c361e8140845ac5a">More...</a><br /></td></tr>
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<tr class="separator:gafb119d6d1955d1b8c361e8140845ac5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee44f159a1ca9ebdd7117bff387cd592"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gaee44f159a1ca9ebdd7117bff387cd592">RCC_AHB3PeriphResetCmd</a> (uint32_t RCC_AHB3Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaee44f159a1ca9ebdd7117bff387cd592"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases AHB3 peripheral reset. <a href="#gaee44f159a1ca9ebdd7117bff387cd592">More...</a><br /></td></tr>
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<tr class="separator:gaee44f159a1ca9ebdd7117bff387cd592"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab197ae4369c10b92640a733b40ed2801"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gab197ae4369c10b92640a733b40ed2801">RCC_APB1PeriphResetCmd</a> (uint32_t RCC_APB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gab197ae4369c10b92640a733b40ed2801"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases Low Speed APB (APB1) peripheral reset. <a href="#gab197ae4369c10b92640a733b40ed2801">More...</a><br /></td></tr>
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<tr class="separator:gab197ae4369c10b92640a733b40ed2801"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad94553850ac07106a27ee85fec37efdf"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#gad94553850ac07106a27ee85fec37efdf">RCC_APB2PeriphResetCmd</a> (uint32_t RCC_APB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gad94553850ac07106a27ee85fec37efdf"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases High Speed APB (APB2) peripheral reset. <a href="#gad94553850ac07106a27ee85fec37efdf">More...</a><br /></td></tr>
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<tr class="separator:gad94553850ac07106a27ee85fec37efdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cd0d5adbc7496d7005b208bd19ce255"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga5cd0d5adbc7496d7005b208bd19ce255">RCC_AHB1PeriphClockLPModeCmd</a> (uint32_t RCC_AHB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga5cd0d5adbc7496d7005b208bd19ce255"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. <a href="#ga5cd0d5adbc7496d7005b208bd19ce255">More...</a><br /></td></tr>
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<tr class="separator:ga5cd0d5adbc7496d7005b208bd19ce255"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ac5bb9676ae9b48e50d6a95de922ce3"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga1ac5bb9676ae9b48e50d6a95de922ce3">RCC_AHB2PeriphClockLPModeCmd</a> (uint32_t RCC_AHB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga1ac5bb9676ae9b48e50d6a95de922ce3"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. <a href="#ga1ac5bb9676ae9b48e50d6a95de922ce3">More...</a><br /></td></tr>
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<tr class="separator:ga1ac5bb9676ae9b48e50d6a95de922ce3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e1df07cdfd81c068902d9d35fcc3911"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga4e1df07cdfd81c068902d9d35fcc3911">RCC_AHB3PeriphClockLPModeCmd</a> (uint32_t RCC_AHB3Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga4e1df07cdfd81c068902d9d35fcc3911"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. <a href="#ga4e1df07cdfd81c068902d9d35fcc3911">More...</a><br /></td></tr>
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<tr class="separator:ga4e1df07cdfd81c068902d9d35fcc3911"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84dd64badb84768cbcf19e241cadff50"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga84dd64badb84768cbcf19e241cadff50">RCC_APB1PeriphClockLPModeCmd</a> (uint32_t RCC_APB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga84dd64badb84768cbcf19e241cadff50"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. <a href="#ga84dd64badb84768cbcf19e241cadff50">More...</a><br /></td></tr>
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<tr class="separator:ga84dd64badb84768cbcf19e241cadff50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30365b9e0b4c5d7e98c2675c862ddd7e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga30365b9e0b4c5d7e98c2675c862ddd7e">RCC_APB2PeriphClockLPModeCmd</a> (uint32_t RCC_APB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga30365b9e0b4c5d7e98c2675c862ddd7e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. <a href="#ga30365b9e0b4c5d7e98c2675c862ddd7e">More...</a><br /></td></tr>
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<tr class="separator:ga30365b9e0b4c5d7e98c2675c862ddd7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1337eb44ba2fce5b3e8ccd92cd01bde4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___group3.html#ga1337eb44ba2fce5b3e8ccd92cd01bde4">RCC_LSEModeConfig</a> (uint8_t Mode)</td></tr>
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<tr class="memdesc:ga1337eb44ba2fce5b3e8ccd92cd01bde4"><td class="mdescLeft"> </td><td class="mdescRight">Configures the External Low Speed oscillator mode (LSE mode). <a href="#ga1337eb44ba2fce5b3e8ccd92cd01bde4">More...</a><br /></td></tr>
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<tr class="separator:ga1337eb44ba2fce5b3e8ccd92cd01bde4"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<p>Peripheral clocks configuration functions. </p>
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<pre class="fragment"> ===============================================================================
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##### Peripheral clocks configuration functions #####
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===============================================================================
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[..] This section provide functions allowing to configure the Peripheral clocks.
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(#) The RTC clock which is derived from the LSI, LSE or HSE clock divided
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by 2 to 31.
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(#) After restart from Reset or wakeup from STANDBY, all peripherals are off
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except internal SRAM, Flash and JTAG. Before to start using a peripheral
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you have to enable its interface clock. You can do this using
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RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
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(#) To reset the peripherals configuration (to the default state after device reset)
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you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
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RCC_APB1PeriphResetCmd() functions.
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(#) To further reduce power consumption in SLEEP mode the peripheral clocks
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can be disabled prior to executing the WFI or WFE instructions.
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You can do this using RCC_AHBPeriphClockLPModeCmd(),
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RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. </pre> <h2 class="groupheader">Function Documentation</h2>
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<a class="anchor" id="ga80c89116820d48bb38db2e7d5e5a49b9"></a>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="memname">void RCC_AHB1PeriphClockCmd </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_AHB1Periph</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the AHB1 peripheral clock. </p>
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<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
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<li>RCC_AHB1Periph_GPIOA: GPIOA clock </li>
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<li>RCC_AHB1Periph_GPIOB: GPIOB clock </li>
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<li>RCC_AHB1Periph_GPIOC: GPIOC clock </li>
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<li>RCC_AHB1Periph_GPIOD: GPIOD clock </li>
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<li>RCC_AHB1Periph_GPIOE: GPIOE clock </li>
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<li>RCC_AHB1Periph_GPIOF: GPIOF clock </li>
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<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
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<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
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<li>RCC_AHB1Periph_GPIOI: GPIOI clock </li>
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<li>RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) </li>
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<li>RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) </li>
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<li>RCC_AHB1Periph_CRC: CRC clock </li>
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<li>RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock </li>
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<li>RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock </li>
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<li>RCC_AHB1Periph_DMA1: DMA1 clock </li>
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<li>RCC_AHB1Periph_DMA2: DMA2 clock </li>
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<li>RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) </li>
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<li>RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock </li>
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<li>RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock </li>
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<li>RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock </li>
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<li>RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock </li>
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<li>RCC_AHB1Periph_OTG_HS: USB OTG HS clock </li>
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<li>RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock </li>
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</ul>
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</td></tr>
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<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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|
<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<p><div class="dynheader">
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<map name="group___r_c_c___group3_ga80c89116820d48bb38db2e7d5e5a49b9_icgraph" id="group___r_c_c___group3_ga80c89116820d48bb38db2e7d5e5a49b9_icgraph">
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<a class="anchor" id="ga5cd0d5adbc7496d7005b208bd19ce255"></a>
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<div class="memitem">
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<tr>
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<td class="memname">void RCC_AHB1PeriphClockLPModeCmd </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_AHB1Periph</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. </p>
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<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
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<dd>
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After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
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<dd>
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By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
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<li>RCC_AHB1Periph_GPIOA: GPIOA clock </li>
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<li>RCC_AHB1Periph_GPIOB: GPIOB clock </li>
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<li>RCC_AHB1Periph_GPIOC: GPIOC clock </li>
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<li>RCC_AHB1Periph_GPIOD: GPIOD clock </li>
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<li>RCC_AHB1Periph_GPIOE: GPIOE clock </li>
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<li>RCC_AHB1Periph_GPIOF: GPIOF clock </li>
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<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
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<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
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<li>RCC_AHB1Periph_GPIOI: GPIOI clock </li>
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<li>RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) </li>
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<li>RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) </li>
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<li>RCC_AHB1Periph_CRC: CRC clock </li>
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<li>RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock </li>
|
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<li>RCC_AHB1Periph_DMA1: DMA1 clock </li>
|
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<li>RCC_AHB1Periph_DMA2: DMA2 clock </li>
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<li>RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) </li>
|
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<li>RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock </li>
|
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<li>RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock </li>
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<li>RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock </li>
|
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<li>RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock </li>
|
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<li>RCC_AHB1Periph_OTG_HS: USB OTG HS clock </li>
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<li>RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock </li>
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</ul>
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</td></tr>
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<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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<a class="anchor" id="gaa7c450567f4731d4f0615f63586cad86"></a>
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<table class="memname">
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<tr>
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<td class="memname">void RCC_AHB1PeriphResetCmd </td>
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<td>(</td>
|
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<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB1Periph</em>, </td>
|
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</tr>
|
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<tr>
|
|
<td class="paramkey"></td>
|
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<td></td>
|
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
|
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Forces or releases AHB1 peripheral reset. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHB1Periph</td><td>specifies the AHB1 peripheral to reset. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_AHB1Periph_GPIOA: GPIOA clock </li>
|
|
<li>RCC_AHB1Periph_GPIOB: GPIOB clock </li>
|
|
<li>RCC_AHB1Periph_GPIOC: GPIOC clock </li>
|
|
<li>RCC_AHB1Periph_GPIOD: GPIOD clock </li>
|
|
<li>RCC_AHB1Periph_GPIOE: GPIOE clock </li>
|
|
<li>RCC_AHB1Periph_GPIOF: GPIOF clock </li>
|
|
<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
|
|
<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
|
|
<li>RCC_AHB1Periph_GPIOI: GPIOI clock </li>
|
|
<li>RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) </li>
|
|
<li>RCC_AHB1Periph_CRC: CRC clock </li>
|
|
<li>RCC_AHB1Periph_DMA1: DMA1 clock </li>
|
|
<li>RCC_AHB1Periph_DMA2: DMA2 clock </li>
|
|
<li>RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) </li>
|
|
<li>RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock </li>
|
|
<li>RCC_AHB1Periph_OTG_HS: USB OTG HS clock</li>
|
|
</ul>
|
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</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
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</table>
|
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
|
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<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void RCC_AHB2PeriphClockCmd </td>
|
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<td>(</td>
|
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<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>RCC_AHB2Periph</em>, </td>
|
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</tr>
|
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<tr>
|
|
<td class="paramkey"></td>
|
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<td></td>
|
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<td class="paramtype">FunctionalState </td>
|
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<td class="paramname"><em>NewState</em> </td>
|
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the AHB2 peripheral clock. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
|
|
<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_AHB2Periph_DCMI: DCMI clock </li>
|
|
<li>RCC_AHB2Periph_CRYP: CRYP clock </li>
|
|
<li>RCC_AHB2Periph_HASH: HASH clock </li>
|
|
<li>RCC_AHB2Periph_RNG: RNG clock </li>
|
|
<li>RCC_AHB2Periph_OTG_FS: USB OTG FS clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
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</table>
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</dd>
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</dl>
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<tr>
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<td class="memname">void RCC_AHB2PeriphClockLPModeCmd </td>
|
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_AHB2Periph</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
|
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. </p>
|
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<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
|
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<dd>
|
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After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
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<dd>
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By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
|
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_AHB2Periph_DCMI: DCMI clock </li>
|
|
<li>RCC_AHB2Periph_CRYP: CRYP clock </li>
|
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<li>RCC_AHB2Periph_HASH: HASH clock </li>
|
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<li>RCC_AHB2Periph_RNG: RNG clock </li>
|
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<li>RCC_AHB2Periph_OTG_FS: USB OTG FS clock </li>
|
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</ul>
|
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</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
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</table>
|
|
</dd>
|
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</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
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</dd>
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</dl>
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</div>
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<a class="anchor" id="gafb119d6d1955d1b8c361e8140845ac5a"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_AHB2PeriphResetCmd </td>
|
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<td>(</td>
|
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<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB2Periph</em>, </td>
|
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</tr>
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<tr>
|
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<td class="paramkey"></td>
|
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Forces or releases AHB2 peripheral reset. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHB2Periph</td><td>specifies the AHB2 peripheral to reset. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_AHB2Periph_DCMI: DCMI clock </li>
|
|
<li>RCC_AHB2Periph_CRYP: CRYP clock </li>
|
|
<li>RCC_AHB2Periph_HASH: HASH clock </li>
|
|
<li>RCC_AHB2Periph_RNG: RNG clock </li>
|
|
<li>RCC_AHB2Periph_OTG_FS: USB OTG FS clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
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</dd>
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</dl>
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<p><div class="dynheader">
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Here is the caller graph for this function:</div>
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<div class="center"><img src="group___r_c_c___group3_gafb119d6d1955d1b8c361e8140845ac5a_icgraph.png" border="0" usemap="#group___r_c_c___group3_gafb119d6d1955d1b8c361e8140845ac5a_icgraph" alt=""/></div>
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<area shape="rect" id="node2" href="group___c_r_y_p___group1.html#gae19e54c9910b697e38f6c7577704ffae" title="Deinitializes the CRYP peripheral registers to their default reset values. " alt="" coords="241,31,340,57"/><area shape="rect" id="node3" href="group___h_a_s_h___group1.html#ga88717fe3a4f557182841a958e1dcd9c7" title="De-initializes the HASH peripheral registers to their default reset values. " alt="" coords="241,81,340,108"/><area shape="rect" id="node8" href="group___r_n_g___group1.html#ga15ff5e649080076eebd51143b9ac4491" title="De-initializes the RNG peripheral registers to their default reset values. " alt="" coords="245,132,336,159"/><area shape="rect" id="node4" href="group___h_a_s_h___group7.html#ga82a155884e458cc6b7c1a4565c1ac8e9" title="Compute the HASH MD5 digest. " alt="" coords="393,5,485,32"/><area shape="rect" id="node5" href="group___h_a_s_h___group7.html#gac61733e7aa66bdd2f21be4b34165b5be" title="Compute the HMAC MD5 digest. " alt="" coords="391,56,486,83"/><area shape="rect" id="node6" href="group___h_a_s_h___group6.html#ga2728c02c36de6d800e1ede56ea7789cb" title="Compute the HASH SHA1 digest. " alt="" coords="389,107,488,133"/><area shape="rect" id="node7" href="group___h_a_s_h___group6.html#ga2e38e900ca7838c1cea17cef19953a5e" title="Compute the HMAC SHA1 digest. " alt="" coords="388,157,489,184"/></map>
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<a class="anchor" id="ga4eb8c119f2e9bf2bd2e042d27f151338"></a>
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<table class="memname">
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<tr>
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<td class="memname">void RCC_AHB3PeriphClockCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB3Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
|
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<td></td><td></td>
|
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</tr>
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</table>
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</div><div class="memdoc">
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|
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<p>Enables or disables the AHB3 peripheral clock. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) </td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
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</div>
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</div>
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<a class="anchor" id="ga4e1df07cdfd81c068902d9d35fcc3911"></a>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="memname">void RCC_AHB3PeriphClockLPModeCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB3Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
|
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<td></td><td></td>
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</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
|
|
<dd>
|
|
After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
|
|
<dd>
|
|
By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices) </td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
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<a class="anchor" id="gaee44f159a1ca9ebdd7117bff387cd592"></a>
|
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<div class="memitem">
|
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<div class="memproto">
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_AHB3PeriphResetCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB3Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
|
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<td></td><td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Forces or releases AHB3 peripheral reset. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHB3Periph</td><td>specifies the AHB3 peripheral to reset. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) </td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
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</div>
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<a class="anchor" id="gaee7cc5d73af7fe1986fceff8afd3973e"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
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<td class="memname">void RCC_APB1PeriphClockCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_APB1Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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|
|
<p>Enables or disables the Low Speed APB (APB1) peripheral clock. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB1Periph</td><td>specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB1Periph_TIM2: TIM2 clock </li>
|
|
<li>RCC_APB1Periph_TIM3: TIM3 clock </li>
|
|
<li>RCC_APB1Periph_TIM4: TIM4 clock </li>
|
|
<li>RCC_APB1Periph_TIM5: TIM5 clock </li>
|
|
<li>RCC_APB1Periph_TIM6: TIM6 clock </li>
|
|
<li>RCC_APB1Periph_TIM7: TIM7 clock </li>
|
|
<li>RCC_APB1Periph_TIM12: TIM12 clock </li>
|
|
<li>RCC_APB1Periph_TIM13: TIM13 clock </li>
|
|
<li>RCC_APB1Periph_TIM14: TIM14 clock </li>
|
|
<li>RCC_APB1Periph_WWDG: WWDG clock </li>
|
|
<li>RCC_APB1Periph_SPI2: SPI2 clock </li>
|
|
<li>RCC_APB1Periph_SPI3: SPI3 clock </li>
|
|
<li>RCC_APB1Periph_USART2: USART2 clock </li>
|
|
<li>RCC_APB1Periph_USART3: USART3 clock </li>
|
|
<li>RCC_APB1Periph_UART4: UART4 clock </li>
|
|
<li>RCC_APB1Periph_UART5: UART5 clock </li>
|
|
<li>RCC_APB1Periph_I2C1: I2C1 clock </li>
|
|
<li>RCC_APB1Periph_I2C2: I2C2 clock </li>
|
|
<li>RCC_APB1Periph_I2C3: I2C3 clock </li>
|
|
<li>RCC_APB1Periph_CAN1: CAN1 clock </li>
|
|
<li>RCC_APB1Periph_CAN2: CAN2 clock </li>
|
|
<li>RCC_APB1Periph_PWR: PWR clock </li>
|
|
<li>RCC_APB1Periph_DAC: DAC clock </li>
|
|
<li>RCC_APB1Periph_UART7: UART7 clock </li>
|
|
<li>RCC_APB1Periph_UART8: UART8 clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
|
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<a class="anchor" id="ga84dd64badb84768cbcf19e241cadff50"></a>
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<div class="memitem">
|
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<div class="memproto">
|
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_APB1PeriphClockLPModeCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_APB1Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
|
|
|
|
<p>Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
|
|
<dd>
|
|
After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
|
|
<dd>
|
|
By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB1Periph</td><td>specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB1Periph_TIM2: TIM2 clock </li>
|
|
<li>RCC_APB1Periph_TIM3: TIM3 clock </li>
|
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<li>RCC_APB1Periph_TIM4: TIM4 clock </li>
|
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<li>RCC_APB1Periph_TIM5: TIM5 clock </li>
|
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<li>RCC_APB1Periph_TIM6: TIM6 clock </li>
|
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<li>RCC_APB1Periph_TIM7: TIM7 clock </li>
|
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<li>RCC_APB1Periph_TIM12: TIM12 clock </li>
|
|
<li>RCC_APB1Periph_TIM13: TIM13 clock </li>
|
|
<li>RCC_APB1Periph_TIM14: TIM14 clock </li>
|
|
<li>RCC_APB1Periph_WWDG: WWDG clock </li>
|
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<li>RCC_APB1Periph_SPI2: SPI2 clock </li>
|
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<li>RCC_APB1Periph_SPI3: SPI3 clock </li>
|
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<li>RCC_APB1Periph_USART2: USART2 clock </li>
|
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<li>RCC_APB1Periph_USART3: USART3 clock </li>
|
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<li>RCC_APB1Periph_UART4: UART4 clock </li>
|
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<li>RCC_APB1Periph_UART5: UART5 clock </li>
|
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<li>RCC_APB1Periph_I2C1: I2C1 clock </li>
|
|
<li>RCC_APB1Periph_I2C2: I2C2 clock </li>
|
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<li>RCC_APB1Periph_I2C3: I2C3 clock </li>
|
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<li>RCC_APB1Periph_CAN1: CAN1 clock </li>
|
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<li>RCC_APB1Periph_CAN2: CAN2 clock </li>
|
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<li>RCC_APB1Periph_PWR: PWR clock </li>
|
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<li>RCC_APB1Periph_DAC: DAC clock </li>
|
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<li>RCC_APB1Periph_UART7: UART7 clock </li>
|
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<li>RCC_APB1Periph_UART8: UART8 clock </li>
|
|
</ul>
|
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</td></tr>
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<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
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</dd>
|
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gab197ae4369c10b92640a733b40ed2801"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_APB1PeriphResetCmd </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_APB1Periph</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Forces or releases Low Speed APB (APB1) peripheral reset. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
|
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<tr><td class="paramname">RCC_APB1Periph</td><td>specifies the APB1 peripheral to reset. This parameter can be any combination of the following values: <ul>
|
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<li>RCC_APB1Periph_TIM2: TIM2 clock </li>
|
|
<li>RCC_APB1Periph_TIM3: TIM3 clock </li>
|
|
<li>RCC_APB1Periph_TIM4: TIM4 clock </li>
|
|
<li>RCC_APB1Periph_TIM5: TIM5 clock </li>
|
|
<li>RCC_APB1Periph_TIM6: TIM6 clock </li>
|
|
<li>RCC_APB1Periph_TIM7: TIM7 clock </li>
|
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<li>RCC_APB1Periph_TIM12: TIM12 clock </li>
|
|
<li>RCC_APB1Periph_TIM13: TIM13 clock </li>
|
|
<li>RCC_APB1Periph_TIM14: TIM14 clock </li>
|
|
<li>RCC_APB1Periph_WWDG: WWDG clock </li>
|
|
<li>RCC_APB1Periph_SPI2: SPI2 clock </li>
|
|
<li>RCC_APB1Periph_SPI3: SPI3 clock </li>
|
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<li>RCC_APB1Periph_USART2: USART2 clock </li>
|
|
<li>RCC_APB1Periph_USART3: USART3 clock </li>
|
|
<li>RCC_APB1Periph_UART4: UART4 clock </li>
|
|
<li>RCC_APB1Periph_UART5: UART5 clock </li>
|
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<li>RCC_APB1Periph_I2C1: I2C1 clock </li>
|
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<li>RCC_APB1Periph_I2C2: I2C2 clock </li>
|
|
<li>RCC_APB1Periph_I2C3: I2C3 clock </li>
|
|
<li>RCC_APB1Periph_CAN1: CAN1 clock </li>
|
|
<li>RCC_APB1Periph_CAN2: CAN2 clock </li>
|
|
<li>RCC_APB1Periph_PWR: PWR clock </li>
|
|
<li>RCC_APB1Periph_DAC: DAC clock </li>
|
|
<li>RCC_APB1Periph_UART7: UART7 clock </li>
|
|
<li>RCC_APB1Periph_UART8: UART8 clock </li>
|
|
</ul>
|
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</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
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|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<area shape="rect" id="node2" href="group___c_a_n___group1.html#ga002b74cd69574a14b17ad445090245cd" title="Deinitializes the CAN peripheral registers to their default reset values. " alt="" coords="251,5,341,32"/><area shape="rect" id="node3" href="group___d_a_c___group1.html#ga1fae225204e1e049d6795319e99ba8bc" title="Deinitializes the DAC peripheral registers to their default reset values. " alt="" coords="251,56,341,83"/><area shape="rect" id="node4" href="group___i2_c___group1.html#ga2ee214364603059ad5d9089f749f5bfd" title="Deinitialize the I2Cx peripheral registers to their default reset values. " alt="" coords="255,107,337,133"/><area shape="rect" id="node5" href="group___p_w_r___group1.html#gad03a0aac7bc3bc3a9fd012f3769a6990" title="Deinitializes the PWR peripheral registers to their default reset values. " alt="" coords="249,157,343,184"/><area shape="rect" id="node6" href="group___s_p_i___group1.html#gabe36880945fa56785283a9c0092124cc" title="De-initialize the SPIx peripheral registers to their default reset values. " alt="" coords="241,208,351,235"/><area shape="rect" id="node7" href="group___t_i_m___group1.html#ga1659cc0ce503ac151568e0c7c02b1ba5" title="Deinitializes the TIMx peripheral registers to their default reset values. " alt="" coords="255,259,337,285"/><area shape="rect" id="node8" href="group___u_s_a_r_t___group1.html#ga2f8e1ce72da21b6539d8e1f299ec3b0d" title="Deinitializes the USARTx peripheral registers to their default reset values. " alt="" coords="243,309,349,336"/><area shape="rect" id="node9" href="group___w_w_d_g___group1.html#ga7130f4dc861b9234b62e73f9f57f89a1" title="Deinitializes the WWDG peripheral registers to their default reset values. " alt="" coords="243,360,349,387"/></map>
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</p>
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<tr>
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<td class="memname">void RCC_APB2PeriphClockCmd </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>RCC_APB2Periph</em>, </td>
|
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</tr>
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<tr>
|
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<td class="paramkey"></td>
|
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<td></td>
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<td class="paramtype">FunctionalState </td>
|
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the High Speed APB (APB2) peripheral clock. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB2Periph</td><td>specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB2Periph_TIM1: TIM1 clock </li>
|
|
<li>RCC_APB2Periph_TIM8: TIM8 clock </li>
|
|
<li>RCC_APB2Periph_USART1: USART1 clock </li>
|
|
<li>RCC_APB2Periph_USART6: USART6 clock </li>
|
|
<li>RCC_APB2Periph_ADC1: ADC1 clock </li>
|
|
<li>RCC_APB2Periph_ADC2: ADC2 clock </li>
|
|
<li>RCC_APB2Periph_ADC3: ADC3 clock </li>
|
|
<li>RCC_APB2Periph_SDIO: SDIO clock </li>
|
|
<li>RCC_APB2Periph_SPI1: SPI1 clock </li>
|
|
<li>RCC_APB2Periph_SPI4: SPI4 clock </li>
|
|
<li>RCC_APB2Periph_SYSCFG: SYSCFG clock </li>
|
|
<li>RCC_APB2Periph_TIM9: TIM9 clock </li>
|
|
<li>RCC_APB2Periph_TIM10: TIM10 clock </li>
|
|
<li>RCC_APB2Periph_TIM11: TIM11 clock </li>
|
|
<li>RCC_APB2Periph_SPI5: SPI5 clock </li>
|
|
<li>RCC_APB2Periph_SPI6: SPI6 clock </li>
|
|
<li>RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<p><div class="dynheader">
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<map name="group___r_c_c___group3_ga56ff55caf8d835351916b40dd030bc87_icgraph" id="group___r_c_c___group3_ga56ff55caf8d835351916b40dd030bc87_icgraph">
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<td class="memname">void RCC_APB2PeriphClockLPModeCmd </td>
|
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<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_APB2Periph</em>, </td>
|
|
</tr>
|
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<tr>
|
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<td class="paramkey"></td>
|
|
<td></td>
|
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<td class="paramtype">FunctionalState </td>
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|
<td class="paramname"><em>NewState</em> </td>
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|
</tr>
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<tr>
|
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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|
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<p>Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
|
|
<dd>
|
|
After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
|
|
<dd>
|
|
By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB2Periph</td><td>specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB2Periph_TIM1: TIM1 clock </li>
|
|
<li>RCC_APB2Periph_TIM8: TIM8 clock </li>
|
|
<li>RCC_APB2Periph_USART1: USART1 clock </li>
|
|
<li>RCC_APB2Periph_USART6: USART6 clock </li>
|
|
<li>RCC_APB2Periph_ADC1: ADC1 clock </li>
|
|
<li>RCC_APB2Periph_ADC2: ADC2 clock </li>
|
|
<li>RCC_APB2Periph_ADC3: ADC3 clock </li>
|
|
<li>RCC_APB2Periph_SDIO: SDIO clock </li>
|
|
<li>RCC_APB2Periph_SPI1: SPI1 clock </li>
|
|
<li>RCC_APB2Periph_SPI4: SPI4 clock </li>
|
|
<li>RCC_APB2Periph_SYSCFG: SYSCFG clock </li>
|
|
<li>RCC_APB2Periph_TIM9: TIM9 clock </li>
|
|
<li>RCC_APB2Periph_TIM10: TIM10 clock </li>
|
|
<li>RCC_APB2Periph_TIM11: TIM11 clock </li>
|
|
<li>RCC_APB2Periph_SPI5: SPI5 clock </li>
|
|
<li>RCC_APB2Periph_SPI6: SPI6 clock </li>
|
|
<li>RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
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</div>
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<a class="anchor" id="gad94553850ac07106a27ee85fec37efdf"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_APB2PeriphResetCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_APB2Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
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<td></td><td></td>
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</tr>
|
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</table>
|
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</div><div class="memdoc">
|
|
|
|
<p>Forces or releases High Speed APB (APB2) peripheral reset. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB2Periph</td><td>specifies the APB2 peripheral to reset. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB2Periph_TIM1: TIM1 clock </li>
|
|
<li>RCC_APB2Periph_TIM8: TIM8 clock </li>
|
|
<li>RCC_APB2Periph_USART1: USART1 clock </li>
|
|
<li>RCC_APB2Periph_USART6: USART6 clock </li>
|
|
<li>RCC_APB2Periph_ADC1: ADC1 clock </li>
|
|
<li>RCC_APB2Periph_ADC2: ADC2 clock </li>
|
|
<li>RCC_APB2Periph_ADC3: ADC3 clock </li>
|
|
<li>RCC_APB2Periph_SDIO: SDIO clock </li>
|
|
<li>RCC_APB2Periph_SPI1: SPI1 clock </li>
|
|
<li>RCC_APB2Periph_SPI4: SPI4 clock </li>
|
|
<li>RCC_APB2Periph_SYSCFG: SYSCFG clock </li>
|
|
<li>RCC_APB2Periph_TIM9: TIM9 clock </li>
|
|
<li>RCC_APB2Periph_TIM10: TIM10 clock </li>
|
|
<li>RCC_APB2Periph_TIM11: TIM11 clock </li>
|
|
<li>RCC_APB2Periph_SPI5: SPI5 clock </li>
|
|
<li>RCC_APB2Periph_SPI6: SPI6 clock </li>
|
|
<li>RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
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<p><div class="dynheader">
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<div class="center"><img src="group___r_c_c___group3_gad94553850ac07106a27ee85fec37efdf_icgraph.png" border="0" usemap="#group___r_c_c___group3_gad94553850ac07106a27ee85fec37efdf_icgraph" alt=""/></div>
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<area shape="rect" id="node2" href="group___a_d_c___group1.html#ga1962afdd9eebe5c896bbba2e4f26fe09" title="Deinitializes all ADCs peripherals registers to their default reset values. " alt="" coords="255,5,344,32"/><area shape="rect" id="node3" href="group___l_t_d_c___group1.html#gad3522837b5ef2b99653e230e649fc149" title="Deinitializes the LTDC peripheral registers to their default reset values. " alt="" coords="253,56,346,83"/><area shape="rect" id="node4" href="group___s_a_i___group1.html#gadcef52be2d2792a70f67b6e7872b334e" title="Deinitialize the SAIx peripheral registers to their default reset values. " alt="" coords="258,107,341,133"/><area shape="rect" id="node5" href="group___s_d_i_o___group1.html#gac359d2c6c67a2590f8f9b720c0e4ff1b" title="Deinitializes the SDIO peripheral registers to their default reset values. " alt="" coords="253,157,346,184"/><area shape="rect" id="node6" href="group___s_p_i___group1.html#gabe36880945fa56785283a9c0092124cc" title="De-initialize the SPIx peripheral registers to their default reset values. " alt="" coords="245,208,354,235"/><area shape="rect" id="node7" href="group___s_y_s_c_f_g___private___functions.html#gaf2f9faa2df9a59a68ae17fae23bc478e" title="Deinitializes the Alternate Functions (remap and EXTI configuration) registers to their default reset..." alt="" coords="241,259,357,285"/><area shape="rect" id="node8" href="group___t_i_m___group1.html#ga1659cc0ce503ac151568e0c7c02b1ba5" title="Deinitializes the TIMx peripheral registers to their default reset values. " alt="" coords="258,309,341,336"/><area shape="rect" id="node9" href="group___u_s_a_r_t___group1.html#ga2f8e1ce72da21b6539d8e1f299ec3b0d" title="Deinitializes the USARTx peripheral registers to their default reset values. " alt="" coords="247,360,352,387"/></map>
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</div>
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</p>
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</div>
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</div>
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<a class="anchor" id="ga636c3b72f35391e67f12a551b15fa54a"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_BackupResetCmd </td>
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<td>(</td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Forces or releases the Backup domain reset. </p>
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<dl class="section note"><dt>Note</dt><dd>This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register. </dd>
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<dd>
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The BKPSRAM is not affected by this reset. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">NewState</td><td>new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga6c56f8529988fcc8f4dbffbc1bab27d0"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_I2SCLKConfig </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_I2SCLKSource</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the I2S clock source (I2SCLK). </p>
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<dl class="section note"><dt>Note</dt><dd>This function must be called before enabling the I2S APB clock. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">RCC_I2SCLKSource</td><td>specifies the I2S clock source. This parameter can be one of the following values: <ul>
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<li>RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source </li>
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<li>RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga1337eb44ba2fce5b3e8ccd92cd01bde4"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_LSEModeConfig </td>
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<td>(</td>
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<td class="paramtype">uint8_t </td>
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<td class="paramname"><em>Mode</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the External Low Speed oscillator mode (LSE mode). </p>
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<dl class="section note"><dt>Note</dt><dd>This mode is only available for STM32F411xx devices. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">Mode</td><td>specifies the LSE mode. This parameter can be one of the following values: <ul>
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<li>RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode. </li>
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<li>RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode. </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gac04a91996aefd2a517cf90c2a44830d2"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_LTDCCLKDivConfig </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_PLLSAIDivR</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the LTDC clock Divider coming from PLLSAI. </p>
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<dl class="section note"><dt>Note</dt><dd>The LTDC peripheral is only available with STM32F429xx/439xx Devices.</dd>
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<dd>
|
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This function must be called before enabling the PLLSAI.</dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">RCC_PLLSAIDivR</td><td>specifies the PLLSAI division factor for LTDC clock . This parameter must be a number between 2 and 16. LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
|
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga9802f84846df2cea8e369234ed13b159"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_RTCCLKCmd </td>
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<td>(</td>
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<td class="paramtype">FunctionalState </td>
|
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<td class="paramname"><em>NewState</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the RTC clock. </p>
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<dl class="section note"><dt>Note</dt><dd>This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function. </dd></dl>
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|
<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">NewState</td><td>new state of the RTC clock. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga1473d8a5a020642966359611c44181b0"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_RTCCLKConfig </td>
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<td>(</td>
|
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<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_RTCCLKSource</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the RTC clock (RTCCLK). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset). </dd>
|
|
<dd>
|
|
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using <a class="el" href="group___r_c_c___group3.html#ga636c3b72f35391e67f12a551b15fa54a" title="Forces or releases the Backup domain reset. ">RCC_BackupResetCmd()</a> function, or by a Power On Reset (POR).</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_RTCCLKSource</td><td>specifies the RTC clock source. This parameter can be one of the following values: <ul>
|
|
<li>RCC_RTCCLKSource_LSE: LSE selected as RTC clock </li>
|
|
<li>RCC_RTCCLKSource_LSI: LSI selected as RTC clock </li>
|
|
<li>RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]</li>
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</ul>
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</td></tr>
|
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</table>
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</dd>
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</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes. </dd>
|
|
<dd>
|
|
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).</dd></dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga6cb4739d834adbf4009112357e1b1099"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_SAIBlockACLKConfig </td>
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<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_SAIBlockACLKSource</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures SAI1BlockA clock source selection. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices.</dd>
|
|
<dd>
|
|
This function must be called before enabling PLLSAI, PLLI2S and the SAI clock. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_SAIBlockACLKSource</td><td>specifies the SAI <a class="el" href="struct_block.html">Block</a> A clock source. This parameter can be one of the following values: <ul>
|
|
<li>RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 <a class="el" href="struct_block.html">Block</a> A clock </li>
|
|
<li>RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 <a class="el" href="struct_block.html">Block</a> A clock </li>
|
|
<li>RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 <a class="el" href="struct_block.html">Block</a> A clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
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</dd>
|
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga4d1fb5c9a743d7f36713c9c76d386557"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_SAIBlockBCLKConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_SAIBlockBCLKSource</em></td><td>)</td>
|
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures SAI1BlockB clock source selection. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices.</dd>
|
|
<dd>
|
|
This function must be called before enabling PLLSAI, PLLI2S and the SAI clock. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_SAIBlockBCLKSource</td><td>specifies the SAI <a class="el" href="struct_block.html">Block</a> B clock source. This parameter can be one of the following values: <ul>
|
|
<li>RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 <a class="el" href="struct_block.html">Block</a> B clock </li>
|
|
<li>RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 <a class="el" href="struct_block.html">Block</a> B clock </li>
|
|
<li>RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 <a class="el" href="struct_block.html">Block</a> B clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga71a887e0e7ef3d49ff87f2cbc435b099"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_SAIPLLI2SClkDivConfig </td>
|
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<td>(</td>
|
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<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>RCC_PLLI2SDivQ</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the SAI clock Divider coming from PLLI2S. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices.</dd>
|
|
<dd>
|
|
This function must be called before enabling the PLLI2S.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_PLLI2SDivQ</td><td>specifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gabefc354915bd57804329349ec3f33fab"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_SAIPLLSAIClkDivConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_PLLSAIDivQ</em></td><td>)</td>
|
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the SAI clock Divider coming from PLLSAI. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices.</dd>
|
|
<dd>
|
|
This function must be called before enabling the PLLSAI.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_PLLSAIDivQ</td><td>specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gaf0599100e7afdf8ed988e351a899e922"></a>
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<div class="memproto">
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<tr>
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<td class="memname">void RCC_TIMCLKPresConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_TIMCLKPrescaler</em></td><td>)</td>
|
|
<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the Timers clocks prescalers selection. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_TIMCLKPrescaler</td><td>: specifies the Timers clocks prescalers selection This parameter can be one of the following values: <ul>
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<li>RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.</li>
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</ul>
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<ul>
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<li>RCC_TIMPrescActivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more. </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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