2832 lines
155 KiB
HTML
2832 lines
155 KiB
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<div class="title">RCC<div class="ingroups"><a class="el" href="group___s_t_m32_f4xx___std_periph___driver.html">STM32F4xx_StdPeriph_Driver</a></div></div> </div>
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Collaboration diagram for RCC:</div>
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<tr class="memitem:group___r_c_c___private___functions"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c___private___functions.html">RCC_Private_Functions</a></td></tr>
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Classes</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_r_c_c___clocks_type_def.html">RCC_ClocksTypeDef</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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Macros</h2></td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>RCC_OFFSET</b>   (RCC_BASE - <a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a>)</td></tr>
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<tr class="separator:ga539e07c3b3c55f1f1d47231341fb11e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa1d3d0ea72132df651c76fc1bdffffc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafa1d3d0ea72132df651c76fc1bdffffc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_OFFSET</b>   (RCC_OFFSET + 0x00)</td></tr>
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<tr class="separator:gafa1d3d0ea72132df651c76fc1bdffffc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3d3085e491cbef815d223afbe5bf1930"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3d3085e491cbef815d223afbe5bf1930"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>HSION_BitNumber</b>   0x00</td></tr>
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<tr class="separator:ga3d3085e491cbef815d223afbe5bf1930"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac3290a833c0e35ec17d32c2d494e6133"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac3290a833c0e35ec17d32c2d494e6133"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_HSION_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (HSION_BitNumber * 4))</td></tr>
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<tr class="separator:gac3290a833c0e35ec17d32c2d494e6133"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga253fa44d87aabc55f0cd6628e77a51fd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga253fa44d87aabc55f0cd6628e77a51fd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CSSON_BitNumber</b>   0x13</td></tr>
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<tr class="separator:ga253fa44d87aabc55f0cd6628e77a51fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaca914aed10477ae4090fea0a9639b1ea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaca914aed10477ae4090fea0a9639b1ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_CSSON_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))</td></tr>
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<tr class="separator:gaca914aed10477ae4090fea0a9639b1ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab24d7f5f8e4b3b717fd91b54f393f6a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab24d7f5f8e4b3b717fd91b54f393f6a3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PLLON_BitNumber</b>   0x18</td></tr>
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<tr class="separator:gab24d7f5f8e4b3b717fd91b54f393f6a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f1fb2589cb8b5ac2f7121aba1135a5f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3f1fb2589cb8b5ac2f7121aba1135a5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_PLLON_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))</td></tr>
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<tr class="separator:ga3f1fb2589cb8b5ac2f7121aba1135a5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabae59c3e4200523e3aa5b6e10aee8c46"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabae59c3e4200523e3aa5b6e10aee8c46"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PLLI2SON_BitNumber</b>   0x1A</td></tr>
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<tr class="separator:gabae59c3e4200523e3aa5b6e10aee8c46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c0fb27aba4eb660f7590252596bdfc5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0c0fb27aba4eb660f7590252596bdfc5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_PLLI2SON_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))</td></tr>
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<tr class="separator:ga0c0fb27aba4eb660f7590252596bdfc5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga786a15b370532d6429e03a9f9d226be7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga786a15b370532d6429e03a9f9d226be7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PLLSAION_BitNumber</b>   0x1C</td></tr>
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<tr class="separator:ga786a15b370532d6429e03a9f9d226be7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab84e7d3874237ee56e5cb3a26644cd13"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab84e7d3874237ee56e5cb3a26644cd13"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_PLLSAION_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))</td></tr>
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<tr class="separator:gab84e7d3874237ee56e5cb3a26644cd13"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8682298330c3b9bae1992e4f1a0af985"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8682298330c3b9bae1992e4f1a0af985"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CFGR_OFFSET</b>   (RCC_OFFSET + 0x08)</td></tr>
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<tr class="separator:ga8682298330c3b9bae1992e4f1a0af985"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9561d436b438d8f513b754f1934c3e30"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9561d436b438d8f513b754f1934c3e30"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2SSRC_BitNumber</b>   0x17</td></tr>
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<tr class="separator:ga9561d436b438d8f513b754f1934c3e30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9076f5ddbb262fd45584702f5d280c9e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9076f5ddbb262fd45584702f5d280c9e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CFGR_I2SSRC_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))</td></tr>
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<tr class="separator:ga9076f5ddbb262fd45584702f5d280c9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5f8a0c3cb5f5c835bf7eef09515138ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5f8a0c3cb5f5c835bf7eef09515138ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>BDCR_OFFSET</b>   (RCC_OFFSET + 0x70)</td></tr>
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<tr class="separator:ga5f8a0c3cb5f5c835bf7eef09515138ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9302c551752124766afc4cee65436405"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9302c551752124766afc4cee65436405"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>RTCEN_BitNumber</b>   0x0F</td></tr>
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<tr class="separator:ga9302c551752124766afc4cee65436405"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf70aaf70b0752ccb3a60307b2fb46038"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf70aaf70b0752ccb3a60307b2fb46038"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>BDCR_RTCEN_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))</td></tr>
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<tr class="separator:gaf70aaf70b0752ccb3a60307b2fb46038"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6718158034388d8fde8caaa28ffe8b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae6718158034388d8fde8caaa28ffe8b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>BDRST_BitNumber</b>   0x10</td></tr>
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<tr class="separator:gae6718158034388d8fde8caaa28ffe8b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga892fdf297b85b85cbaf0723649b31818"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga892fdf297b85b85cbaf0723649b31818"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>BDCR_BDRST_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))</td></tr>
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<tr class="separator:ga892fdf297b85b85cbaf0723649b31818"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga984cbe73312b6d3d355c5053763d499a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga984cbe73312b6d3d355c5053763d499a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CSR_OFFSET</b>   (RCC_OFFSET + 0x74)</td></tr>
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<tr class="separator:ga984cbe73312b6d3d355c5053763d499a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3f9dbe50769ce2a63ae12520433b9b40"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3f9dbe50769ce2a63ae12520433b9b40"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>LSION_BitNumber</b>   0x00</td></tr>
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<tr class="separator:ga3f9dbe50769ce2a63ae12520433b9b40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa253e36e7e5fb02998c0e4d0388abc52"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa253e36e7e5fb02998c0e4d0388abc52"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CSR_LSION_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))</td></tr>
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<tr class="separator:gaa253e36e7e5fb02998c0e4d0388abc52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga622e592eac9f955633832687cb4aacbd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga622e592eac9f955633832687cb4aacbd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DCKCFGR_OFFSET</b>   (RCC_OFFSET + 0x8C)</td></tr>
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<tr class="separator:ga622e592eac9f955633832687cb4aacbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e4d33566ef60a5220ce491e74a34478"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3e4d33566ef60a5220ce491e74a34478"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>TIMPRE_BitNumber</b>   0x18</td></tr>
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<tr class="separator:ga3e4d33566ef60a5220ce491e74a34478"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaff212f4f5168f26347acf1abbb331961"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaff212f4f5168f26347acf1abbb331961"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DCKCFGR_TIMPRE_BB</b>   (<a class="el" href="group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a">PERIPH_BB_BASE</a> + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))</td></tr>
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<tr class="separator:gaff212f4f5168f26347acf1abbb331961"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabd7dd9cf31a9cc27fd9c0c1624f9a298"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabd7dd9cf31a9cc27fd9c0c1624f9a298"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CFGR_MCO2_RESET_MASK</b>   ((uint32_t)0x07FFFFFF)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CFGR_MCO1_RESET_MASK</b>   ((uint32_t)0xF89FFFFF)</td></tr>
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<tr class="memitem:ga890221cb651a3f30f6d1bca0d9b0e13d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga890221cb651a3f30f6d1bca0d9b0e13d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>FLAG_MASK</b>   ((uint8_t)0x1F)</td></tr>
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<tr class="memitem:ga9b2724575bb34217aeddcb69c41a1547"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9b2724575bb34217aeddcb69c41a1547"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CR_BYTE3_ADDRESS</b>   ((uint32_t)0x40023802)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CIR_BYTE2_ADDRESS</b>   ((uint32_t)(RCC_BASE + 0x0C + 0x01))</td></tr>
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<tr class="memitem:ga43f47430582c9575970901533e525bb5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga43f47430582c9575970901533e525bb5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CIR_BYTE3_ADDRESS</b>   ((uint32_t)(RCC_BASE + 0x0C + 0x02))</td></tr>
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<tr class="memitem:ga40b5a415d697b6af7babd8a208c92435"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga40b5a415d697b6af7babd8a208c92435"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>BDCR_ADDRESS</b>   (<a class="el" href="group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0">PERIPH_BASE</a> + BDCR_OFFSET)</td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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Functions</h2></td></tr>
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<tr class="memitem:ga413f6422be11b1334abe60b3bff2e062"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga413f6422be11b1334abe60b3bff2e062">RCC_DeInit</a> (void)</td></tr>
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<tr class="memdesc:ga413f6422be11b1334abe60b3bff2e062"><td class="mdescLeft"> </td><td class="mdescRight">Resets the RCC clock configuration to the default reset state. <a href="#ga413f6422be11b1334abe60b3bff2e062">More...</a><br /></td></tr>
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<tr class="separator:ga413f6422be11b1334abe60b3bff2e062"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga523b06e73f6aa8a03e42299c855066a8"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga523b06e73f6aa8a03e42299c855066a8">RCC_HSEConfig</a> (uint8_t RCC_HSE)</td></tr>
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<tr class="memdesc:ga523b06e73f6aa8a03e42299c855066a8"><td class="mdescLeft"> </td><td class="mdescRight">Configures the External High Speed oscillator (HSE). <a href="#ga523b06e73f6aa8a03e42299c855066a8">More...</a><br /></td></tr>
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<tr class="separator:ga523b06e73f6aa8a03e42299c855066a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae0f15692614dd048ee4110a056f001dc"><td class="memItemLeft" align="right" valign="top">ErrorStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gae0f15692614dd048ee4110a056f001dc">RCC_WaitForHSEStartUp</a> (void)</td></tr>
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<tr class="memdesc:gae0f15692614dd048ee4110a056f001dc"><td class="mdescLeft"> </td><td class="mdescRight">Waits for HSE start-up. <a href="#gae0f15692614dd048ee4110a056f001dc">More...</a><br /></td></tr>
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<tr class="separator:gae0f15692614dd048ee4110a056f001dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa2d6a35f5c2e0f86317c3beb222677fc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaa2d6a35f5c2e0f86317c3beb222677fc">RCC_AdjustHSICalibrationValue</a> (uint8_t HSICalibrationValue)</td></tr>
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<tr class="memdesc:gaa2d6a35f5c2e0f86317c3beb222677fc"><td class="mdescLeft"> </td><td class="mdescRight">Adjusts the Internal High Speed oscillator (HSI) calibration value. <a href="#gaa2d6a35f5c2e0f86317c3beb222677fc">More...</a><br /></td></tr>
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<tr class="separator:gaa2d6a35f5c2e0f86317c3beb222677fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0c6772a1e43765909495f57815ef69e2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga0c6772a1e43765909495f57815ef69e2">RCC_HSICmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga0c6772a1e43765909495f57815ef69e2"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Internal High Speed oscillator (HSI). <a href="#ga0c6772a1e43765909495f57815ef69e2">More...</a><br /></td></tr>
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<tr class="separator:ga0c6772a1e43765909495f57815ef69e2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga65209ab5c3589b249c7d70f978735ca6"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga65209ab5c3589b249c7d70f978735ca6">RCC_LSEConfig</a> (uint8_t RCC_LSE)</td></tr>
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<tr class="memdesc:ga65209ab5c3589b249c7d70f978735ca6"><td class="mdescLeft"> </td><td class="mdescRight">Configures the External Low Speed oscillator (LSE). <a href="#ga65209ab5c3589b249c7d70f978735ca6">More...</a><br /></td></tr>
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<tr class="separator:ga65209ab5c3589b249c7d70f978735ca6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga81e3ca29fd154ac2019bba6936d6d5ed"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga81e3ca29fd154ac2019bba6936d6d5ed">RCC_LSICmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga81e3ca29fd154ac2019bba6936d6d5ed"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Internal Low Speed oscillator (LSI). <a href="#ga81e3ca29fd154ac2019bba6936d6d5ed">More...</a><br /></td></tr>
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<tr class="separator:ga81e3ca29fd154ac2019bba6936d6d5ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga154b93e90bfdede2a874244a1ff1002e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga154b93e90bfdede2a874244a1ff1002e">RCC_PLLConfig</a> (uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)</td></tr>
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<tr class="memdesc:ga154b93e90bfdede2a874244a1ff1002e"><td class="mdescLeft"> </td><td class="mdescRight">Configures the main PLL clock source, multiplication and division factors. <a href="#ga154b93e90bfdede2a874244a1ff1002e">More...</a><br /></td></tr>
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<tr class="separator:ga154b93e90bfdede2a874244a1ff1002e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84dee53c75e58fdb53571716593c2272"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga84dee53c75e58fdb53571716593c2272">RCC_PLLCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga84dee53c75e58fdb53571716593c2272"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the main PLL. <a href="#ga84dee53c75e58fdb53571716593c2272">More...</a><br /></td></tr>
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<tr class="separator:ga84dee53c75e58fdb53571716593c2272"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4c15157382939a693c15620a4867e6ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4c15157382939a693c15620a4867e6ad"></a>
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void </td><td class="memItemRight" valign="bottom"><b>RCC_PLLI2SConfig</b> (uint32_t PLLI2SN, uint32_t PLLI2SR)</td></tr>
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<tr class="separator:ga4c15157382939a693c15620a4867e6ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2efe493a6337d5e0034bfcdfb0f541e4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga2efe493a6337d5e0034bfcdfb0f541e4">RCC_PLLI2SCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga2efe493a6337d5e0034bfcdfb0f541e4"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the PLLI2S. <a href="#ga2efe493a6337d5e0034bfcdfb0f541e4">More...</a><br /></td></tr>
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<tr class="separator:ga2efe493a6337d5e0034bfcdfb0f541e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaed7cbf4255d155c78a714a70752d14bf"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaed7cbf4255d155c78a714a70752d14bf">RCC_PLLSAIConfig</a> (uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)</td></tr>
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<tr class="memdesc:gaed7cbf4255d155c78a714a70752d14bf"><td class="mdescLeft"> </td><td class="mdescRight">Configures the PLLSAI clock multiplication and division factors. <a href="#gaed7cbf4255d155c78a714a70752d14bf">More...</a><br /></td></tr>
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<tr class="separator:gaed7cbf4255d155c78a714a70752d14bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf7b2c8f7533c8321dce97196d9f77fc1"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaf7b2c8f7533c8321dce97196d9f77fc1">RCC_PLLSAICmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaf7b2c8f7533c8321dce97196d9f77fc1"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the PLLSAI. <a href="#gaf7b2c8f7533c8321dce97196d9f77fc1">More...</a><br /></td></tr>
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<tr class="separator:gaf7b2c8f7533c8321dce97196d9f77fc1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga0ff1fd7b9a8a49cdda11b7d7261c3494"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga0ff1fd7b9a8a49cdda11b7d7261c3494">RCC_ClockSecuritySystemCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga0ff1fd7b9a8a49cdda11b7d7261c3494"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Clock Security System. <a href="#ga0ff1fd7b9a8a49cdda11b7d7261c3494">More...</a><br /></td></tr>
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<tr class="separator:ga0ff1fd7b9a8a49cdda11b7d7261c3494"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga15c9ecb6ef015ed008cb28e5b7a50531"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga15c9ecb6ef015ed008cb28e5b7a50531">RCC_MCO1Config</a> (uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)</td></tr>
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<tr class="memdesc:ga15c9ecb6ef015ed008cb28e5b7a50531"><td class="mdescLeft"> </td><td class="mdescRight">Selects the clock source to output on MCO1 pin(PA8). <a href="#ga15c9ecb6ef015ed008cb28e5b7a50531">More...</a><br /></td></tr>
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<tr class="separator:ga15c9ecb6ef015ed008cb28e5b7a50531"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf50f10675b747de60c739e44e5c22aee"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaf50f10675b747de60c739e44e5c22aee">RCC_MCO2Config</a> (uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)</td></tr>
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<tr class="memdesc:gaf50f10675b747de60c739e44e5c22aee"><td class="mdescLeft"> </td><td class="mdescRight">Selects the clock source to output on MCO2 pin(PC9). <a href="#gaf50f10675b747de60c739e44e5c22aee">More...</a><br /></td></tr>
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<tr class="separator:gaf50f10675b747de60c739e44e5c22aee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3551a36a8f0a3dc96a74d6b939048337"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga3551a36a8f0a3dc96a74d6b939048337">RCC_SYSCLKConfig</a> (uint32_t RCC_SYSCLKSource)</td></tr>
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<tr class="memdesc:ga3551a36a8f0a3dc96a74d6b939048337"><td class="mdescLeft"> </td><td class="mdescRight">Configures the system clock (SYSCLK). <a href="#ga3551a36a8f0a3dc96a74d6b939048337">More...</a><br /></td></tr>
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<tr class="separator:ga3551a36a8f0a3dc96a74d6b939048337"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaaeb32311c208b2a980841c9c884a41ea"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaaeb32311c208b2a980841c9c884a41ea">RCC_GetSYSCLKSource</a> (void)</td></tr>
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<tr class="memdesc:gaaeb32311c208b2a980841c9c884a41ea"><td class="mdescLeft"> </td><td class="mdescRight">Returns the clock source used as system clock. <a href="#gaaeb32311c208b2a980841c9c884a41ea">More...</a><br /></td></tr>
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<tr class="separator:gaaeb32311c208b2a980841c9c884a41ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9d0aec72e236c6cdf3a3a82dfb525491"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga9d0aec72e236c6cdf3a3a82dfb525491">RCC_HCLKConfig</a> (uint32_t RCC_SYSCLK)</td></tr>
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<tr class="memdesc:ga9d0aec72e236c6cdf3a3a82dfb525491"><td class="mdescLeft"> </td><td class="mdescRight">Configures the AHB clock (HCLK). <a href="#ga9d0aec72e236c6cdf3a3a82dfb525491">More...</a><br /></td></tr>
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<tr class="separator:ga9d0aec72e236c6cdf3a3a82dfb525491"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga448137346d4292985d4e7a61dd1a824f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga448137346d4292985d4e7a61dd1a824f">RCC_PCLK1Config</a> (uint32_t RCC_HCLK)</td></tr>
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<tr class="memdesc:ga448137346d4292985d4e7a61dd1a824f"><td class="mdescLeft"> </td><td class="mdescRight">Configures the Low Speed APB clock (PCLK1). <a href="#ga448137346d4292985d4e7a61dd1a824f">More...</a><br /></td></tr>
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<tr class="separator:ga448137346d4292985d4e7a61dd1a824f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga09f9c010a4adca9e036da42c2ca6126a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga09f9c010a4adca9e036da42c2ca6126a">RCC_PCLK2Config</a> (uint32_t RCC_HCLK)</td></tr>
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<tr class="memdesc:ga09f9c010a4adca9e036da42c2ca6126a"><td class="mdescLeft"> </td><td class="mdescRight">Configures the High Speed APB clock (PCLK2). <a href="#ga09f9c010a4adca9e036da42c2ca6126a">More...</a><br /></td></tr>
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<tr class="separator:ga09f9c010a4adca9e036da42c2ca6126a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga3e9944fd1ed734275222bbb3e3f29993"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga3e9944fd1ed734275222bbb3e3f29993">RCC_GetClocksFreq</a> (<a class="el" href="struct_r_c_c___clocks_type_def.html">RCC_ClocksTypeDef</a> *RCC_Clocks)</td></tr>
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<tr class="memdesc:ga3e9944fd1ed734275222bbb3e3f29993"><td class="mdescLeft"> </td><td class="mdescRight">Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. <a href="#ga3e9944fd1ed734275222bbb3e3f29993">More...</a><br /></td></tr>
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<tr class="separator:ga3e9944fd1ed734275222bbb3e3f29993"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1473d8a5a020642966359611c44181b0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga1473d8a5a020642966359611c44181b0">RCC_RTCCLKConfig</a> (uint32_t RCC_RTCCLKSource)</td></tr>
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<tr class="memdesc:ga1473d8a5a020642966359611c44181b0"><td class="mdescLeft"> </td><td class="mdescRight">Configures the RTC clock (RTCCLK). <a href="#ga1473d8a5a020642966359611c44181b0">More...</a><br /></td></tr>
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<tr class="separator:ga1473d8a5a020642966359611c44181b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9802f84846df2cea8e369234ed13b159"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga9802f84846df2cea8e369234ed13b159">RCC_RTCCLKCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga9802f84846df2cea8e369234ed13b159"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the RTC clock. <a href="#ga9802f84846df2cea8e369234ed13b159">More...</a><br /></td></tr>
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<tr class="separator:ga9802f84846df2cea8e369234ed13b159"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga636c3b72f35391e67f12a551b15fa54a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga636c3b72f35391e67f12a551b15fa54a">RCC_BackupResetCmd</a> (FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga636c3b72f35391e67f12a551b15fa54a"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases the Backup domain reset. <a href="#ga636c3b72f35391e67f12a551b15fa54a">More...</a><br /></td></tr>
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<tr class="separator:ga636c3b72f35391e67f12a551b15fa54a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6c56f8529988fcc8f4dbffbc1bab27d0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga6c56f8529988fcc8f4dbffbc1bab27d0">RCC_I2SCLKConfig</a> (uint32_t RCC_I2SCLKSource)</td></tr>
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<tr class="memdesc:ga6c56f8529988fcc8f4dbffbc1bab27d0"><td class="mdescLeft"> </td><td class="mdescRight">Configures the I2S clock source (I2SCLK). <a href="#ga6c56f8529988fcc8f4dbffbc1bab27d0">More...</a><br /></td></tr>
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<tr class="separator:ga6c56f8529988fcc8f4dbffbc1bab27d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga71a887e0e7ef3d49ff87f2cbc435b099"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga71a887e0e7ef3d49ff87f2cbc435b099">RCC_SAIPLLI2SClkDivConfig</a> (uint32_t RCC_PLLI2SDivQ)</td></tr>
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<tr class="memdesc:ga71a887e0e7ef3d49ff87f2cbc435b099"><td class="mdescLeft"> </td><td class="mdescRight">Configures the SAI clock Divider coming from PLLI2S. <a href="#ga71a887e0e7ef3d49ff87f2cbc435b099">More...</a><br /></td></tr>
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<tr class="separator:ga71a887e0e7ef3d49ff87f2cbc435b099"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabefc354915bd57804329349ec3f33fab"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gabefc354915bd57804329349ec3f33fab">RCC_SAIPLLSAIClkDivConfig</a> (uint32_t RCC_PLLSAIDivQ)</td></tr>
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<tr class="memdesc:gabefc354915bd57804329349ec3f33fab"><td class="mdescLeft"> </td><td class="mdescRight">Configures the SAI clock Divider coming from PLLSAI. <a href="#gabefc354915bd57804329349ec3f33fab">More...</a><br /></td></tr>
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<tr class="separator:gabefc354915bd57804329349ec3f33fab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6cb4739d834adbf4009112357e1b1099"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga6cb4739d834adbf4009112357e1b1099">RCC_SAIBlockACLKConfig</a> (uint32_t RCC_SAIBlockACLKSource)</td></tr>
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<tr class="memdesc:ga6cb4739d834adbf4009112357e1b1099"><td class="mdescLeft"> </td><td class="mdescRight">Configures SAI1BlockA clock source selection. <a href="#ga6cb4739d834adbf4009112357e1b1099">More...</a><br /></td></tr>
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<tr class="separator:ga6cb4739d834adbf4009112357e1b1099"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4d1fb5c9a743d7f36713c9c76d386557"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga4d1fb5c9a743d7f36713c9c76d386557">RCC_SAIBlockBCLKConfig</a> (uint32_t RCC_SAIBlockBCLKSource)</td></tr>
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<tr class="memdesc:ga4d1fb5c9a743d7f36713c9c76d386557"><td class="mdescLeft"> </td><td class="mdescRight">Configures SAI1BlockB clock source selection. <a href="#ga4d1fb5c9a743d7f36713c9c76d386557">More...</a><br /></td></tr>
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<tr class="separator:ga4d1fb5c9a743d7f36713c9c76d386557"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac04a91996aefd2a517cf90c2a44830d2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gac04a91996aefd2a517cf90c2a44830d2">RCC_LTDCCLKDivConfig</a> (uint32_t RCC_PLLSAIDivR)</td></tr>
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<tr class="memdesc:gac04a91996aefd2a517cf90c2a44830d2"><td class="mdescLeft"> </td><td class="mdescRight">Configures the LTDC clock Divider coming from PLLSAI. <a href="#gac04a91996aefd2a517cf90c2a44830d2">More...</a><br /></td></tr>
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<tr class="separator:gac04a91996aefd2a517cf90c2a44830d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf0599100e7afdf8ed988e351a899e922"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaf0599100e7afdf8ed988e351a899e922">RCC_TIMCLKPresConfig</a> (uint32_t RCC_TIMCLKPrescaler)</td></tr>
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<tr class="memdesc:gaf0599100e7afdf8ed988e351a899e922"><td class="mdescLeft"> </td><td class="mdescRight">Configures the Timers clocks prescalers selection. <a href="#gaf0599100e7afdf8ed988e351a899e922">More...</a><br /></td></tr>
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<tr class="separator:gaf0599100e7afdf8ed988e351a899e922"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga80c89116820d48bb38db2e7d5e5a49b9"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga80c89116820d48bb38db2e7d5e5a49b9">RCC_AHB1PeriphClockCmd</a> (uint32_t RCC_AHB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga80c89116820d48bb38db2e7d5e5a49b9"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB1 peripheral clock. <a href="#ga80c89116820d48bb38db2e7d5e5a49b9">More...</a><br /></td></tr>
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<tr class="separator:ga80c89116820d48bb38db2e7d5e5a49b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaadffedbd87e796f01d9776b8ee01ff5e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaadffedbd87e796f01d9776b8ee01ff5e">RCC_AHB2PeriphClockCmd</a> (uint32_t RCC_AHB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaadffedbd87e796f01d9776b8ee01ff5e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB2 peripheral clock. <a href="#gaadffedbd87e796f01d9776b8ee01ff5e">More...</a><br /></td></tr>
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<tr class="separator:gaadffedbd87e796f01d9776b8ee01ff5e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4eb8c119f2e9bf2bd2e042d27f151338"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga4eb8c119f2e9bf2bd2e042d27f151338">RCC_AHB3PeriphClockCmd</a> (uint32_t RCC_AHB3Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga4eb8c119f2e9bf2bd2e042d27f151338"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB3 peripheral clock. <a href="#ga4eb8c119f2e9bf2bd2e042d27f151338">More...</a><br /></td></tr>
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<tr class="separator:ga4eb8c119f2e9bf2bd2e042d27f151338"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee7cc5d73af7fe1986fceff8afd3973e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaee7cc5d73af7fe1986fceff8afd3973e">RCC_APB1PeriphClockCmd</a> (uint32_t RCC_APB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaee7cc5d73af7fe1986fceff8afd3973e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the Low Speed APB (APB1) peripheral clock. <a href="#gaee7cc5d73af7fe1986fceff8afd3973e">More...</a><br /></td></tr>
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<tr class="separator:gaee7cc5d73af7fe1986fceff8afd3973e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga56ff55caf8d835351916b40dd030bc87"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga56ff55caf8d835351916b40dd030bc87">RCC_APB2PeriphClockCmd</a> (uint32_t RCC_APB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga56ff55caf8d835351916b40dd030bc87"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the High Speed APB (APB2) peripheral clock. <a href="#ga56ff55caf8d835351916b40dd030bc87">More...</a><br /></td></tr>
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<tr class="separator:ga56ff55caf8d835351916b40dd030bc87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa7c450567f4731d4f0615f63586cad86"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaa7c450567f4731d4f0615f63586cad86">RCC_AHB1PeriphResetCmd</a> (uint32_t RCC_AHB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaa7c450567f4731d4f0615f63586cad86"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases AHB1 peripheral reset. <a href="#gaa7c450567f4731d4f0615f63586cad86">More...</a><br /></td></tr>
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<tr class="separator:gaa7c450567f4731d4f0615f63586cad86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafb119d6d1955d1b8c361e8140845ac5a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gafb119d6d1955d1b8c361e8140845ac5a">RCC_AHB2PeriphResetCmd</a> (uint32_t RCC_AHB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gafb119d6d1955d1b8c361e8140845ac5a"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases AHB2 peripheral reset. <a href="#gafb119d6d1955d1b8c361e8140845ac5a">More...</a><br /></td></tr>
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<tr class="separator:gafb119d6d1955d1b8c361e8140845ac5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaee44f159a1ca9ebdd7117bff387cd592"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaee44f159a1ca9ebdd7117bff387cd592">RCC_AHB3PeriphResetCmd</a> (uint32_t RCC_AHB3Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaee44f159a1ca9ebdd7117bff387cd592"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases AHB3 peripheral reset. <a href="#gaee44f159a1ca9ebdd7117bff387cd592">More...</a><br /></td></tr>
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<tr class="separator:gaee44f159a1ca9ebdd7117bff387cd592"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab197ae4369c10b92640a733b40ed2801"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gab197ae4369c10b92640a733b40ed2801">RCC_APB1PeriphResetCmd</a> (uint32_t RCC_APB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gab197ae4369c10b92640a733b40ed2801"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases Low Speed APB (APB1) peripheral reset. <a href="#gab197ae4369c10b92640a733b40ed2801">More...</a><br /></td></tr>
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<tr class="separator:gab197ae4369c10b92640a733b40ed2801"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad94553850ac07106a27ee85fec37efdf"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gad94553850ac07106a27ee85fec37efdf">RCC_APB2PeriphResetCmd</a> (uint32_t RCC_APB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gad94553850ac07106a27ee85fec37efdf"><td class="mdescLeft"> </td><td class="mdescRight">Forces or releases High Speed APB (APB2) peripheral reset. <a href="#gad94553850ac07106a27ee85fec37efdf">More...</a><br /></td></tr>
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<tr class="separator:gad94553850ac07106a27ee85fec37efdf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga5cd0d5adbc7496d7005b208bd19ce255"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga5cd0d5adbc7496d7005b208bd19ce255">RCC_AHB1PeriphClockLPModeCmd</a> (uint32_t RCC_AHB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga5cd0d5adbc7496d7005b208bd19ce255"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. <a href="#ga5cd0d5adbc7496d7005b208bd19ce255">More...</a><br /></td></tr>
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<tr class="separator:ga5cd0d5adbc7496d7005b208bd19ce255"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1ac5bb9676ae9b48e50d6a95de922ce3"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga1ac5bb9676ae9b48e50d6a95de922ce3">RCC_AHB2PeriphClockLPModeCmd</a> (uint32_t RCC_AHB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga1ac5bb9676ae9b48e50d6a95de922ce3"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. <a href="#ga1ac5bb9676ae9b48e50d6a95de922ce3">More...</a><br /></td></tr>
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<tr class="separator:ga1ac5bb9676ae9b48e50d6a95de922ce3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4e1df07cdfd81c068902d9d35fcc3911"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga4e1df07cdfd81c068902d9d35fcc3911">RCC_AHB3PeriphClockLPModeCmd</a> (uint32_t RCC_AHB3Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga4e1df07cdfd81c068902d9d35fcc3911"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. <a href="#ga4e1df07cdfd81c068902d9d35fcc3911">More...</a><br /></td></tr>
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<tr class="separator:ga4e1df07cdfd81c068902d9d35fcc3911"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga84dd64badb84768cbcf19e241cadff50"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga84dd64badb84768cbcf19e241cadff50">RCC_APB1PeriphClockLPModeCmd</a> (uint32_t RCC_APB1Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga84dd64badb84768cbcf19e241cadff50"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. <a href="#ga84dd64badb84768cbcf19e241cadff50">More...</a><br /></td></tr>
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<tr class="separator:ga84dd64badb84768cbcf19e241cadff50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga30365b9e0b4c5d7e98c2675c862ddd7e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga30365b9e0b4c5d7e98c2675c862ddd7e">RCC_APB2PeriphClockLPModeCmd</a> (uint32_t RCC_APB2Periph, FunctionalState NewState)</td></tr>
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<tr class="memdesc:ga30365b9e0b4c5d7e98c2675c862ddd7e"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. <a href="#ga30365b9e0b4c5d7e98c2675c862ddd7e">More...</a><br /></td></tr>
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<tr class="separator:ga30365b9e0b4c5d7e98c2675c862ddd7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1337eb44ba2fce5b3e8ccd92cd01bde4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga1337eb44ba2fce5b3e8ccd92cd01bde4">RCC_LSEModeConfig</a> (uint8_t Mode)</td></tr>
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<tr class="memdesc:ga1337eb44ba2fce5b3e8ccd92cd01bde4"><td class="mdescLeft"> </td><td class="mdescRight">Configures the External Low Speed oscillator mode (LSE mode). <a href="#ga1337eb44ba2fce5b3e8ccd92cd01bde4">More...</a><br /></td></tr>
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<tr class="separator:ga1337eb44ba2fce5b3e8ccd92cd01bde4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaa953aa226e9ce45300d535941e4dfe2f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#gaa953aa226e9ce45300d535941e4dfe2f">RCC_ITConfig</a> (uint8_t RCC_IT, FunctionalState NewState)</td></tr>
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<tr class="memdesc:gaa953aa226e9ce45300d535941e4dfe2f"><td class="mdescLeft"> </td><td class="mdescRight">Enables or disables the specified RCC interrupts. <a href="#gaa953aa226e9ce45300d535941e4dfe2f">More...</a><br /></td></tr>
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<tr class="separator:gaa953aa226e9ce45300d535941e4dfe2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga2897bdc52f272031c44fb1f72205d295"><td class="memItemLeft" align="right" valign="top">FlagStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga2897bdc52f272031c44fb1f72205d295">RCC_GetFlagStatus</a> (uint8_t RCC_FLAG)</td></tr>
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<tr class="memdesc:ga2897bdc52f272031c44fb1f72205d295"><td class="mdescLeft"> </td><td class="mdescRight">Checks whether the specified RCC flag is set or not. <a href="#ga2897bdc52f272031c44fb1f72205d295">More...</a><br /></td></tr>
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<tr class="separator:ga2897bdc52f272031c44fb1f72205d295"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga53f909dbb15a54124419084ebda97d72"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga53f909dbb15a54124419084ebda97d72">RCC_ClearFlag</a> (void)</td></tr>
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<tr class="memdesc:ga53f909dbb15a54124419084ebda97d72"><td class="mdescLeft"> </td><td class="mdescRight">Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. <a href="#ga53f909dbb15a54124419084ebda97d72">More...</a><br /></td></tr>
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<tr class="separator:ga53f909dbb15a54124419084ebda97d72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga6126c99f398ee4be410ad76ae3aee18f"><td class="memItemLeft" align="right" valign="top">ITStatus </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga6126c99f398ee4be410ad76ae3aee18f">RCC_GetITStatus</a> (uint8_t RCC_IT)</td></tr>
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<tr class="memdesc:ga6126c99f398ee4be410ad76ae3aee18f"><td class="mdescLeft"> </td><td class="mdescRight">Checks whether the specified RCC interrupt has occurred or not. <a href="#ga6126c99f398ee4be410ad76ae3aee18f">More...</a><br /></td></tr>
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<tr class="separator:ga6126c99f398ee4be410ad76ae3aee18f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga529842d165910f8f87e26115da36089b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___r_c_c.html#ga529842d165910f8f87e26115da36089b">RCC_ClearITPendingBit</a> (uint8_t RCC_IT)</td></tr>
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<tr class="memdesc:ga529842d165910f8f87e26115da36089b"><td class="mdescLeft"> </td><td class="mdescRight">Clears the RCC's interrupt pending bits. <a href="#ga529842d165910f8f87e26115da36089b">More...</a><br /></td></tr>
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<tr class="separator:ga529842d165910f8f87e26115da36089b"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<p>RCC driver modules. </p>
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<h2 class="groupheader">Function Documentation</h2>
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<a class="anchor" id="gaa2d6a35f5c2e0f86317c3beb222677fc"></a>
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<tr>
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<td class="memname">void RCC_AdjustHSICalibrationValue </td>
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<td>(</td>
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<td class="paramtype">uint8_t </td>
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<td class="paramname"><em>HSICalibrationValue</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Adjusts the Internal High Speed oscillator (HSI) calibration value. </p>
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<dl class="section note"><dt>Note</dt><dd>The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">HSICalibrationValue</td><td>specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void RCC_AHB1PeriphClockCmd </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_AHB1Periph</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the AHB1 peripheral clock. </p>
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<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
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<li>RCC_AHB1Periph_GPIOA: GPIOA clock </li>
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<li>RCC_AHB1Periph_GPIOB: GPIOB clock </li>
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<li>RCC_AHB1Periph_GPIOC: GPIOC clock </li>
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<li>RCC_AHB1Periph_GPIOD: GPIOD clock </li>
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<li>RCC_AHB1Periph_GPIOE: GPIOE clock </li>
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<li>RCC_AHB1Periph_GPIOF: GPIOF clock </li>
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<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
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<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
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<li>RCC_AHB1Periph_GPIOI: GPIOI clock </li>
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<li>RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) </li>
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<li>RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) </li>
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<li>RCC_AHB1Periph_CRC: CRC clock </li>
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<li>RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock </li>
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<li>RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock </li>
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<li>RCC_AHB1Periph_DMA1: DMA1 clock </li>
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<li>RCC_AHB1Periph_DMA2: DMA2 clock </li>
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<li>RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) </li>
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<li>RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock </li>
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<li>RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock </li>
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<li>RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock </li>
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<li>RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock </li>
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<li>RCC_AHB1Periph_OTG_HS: USB OTG HS clock </li>
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<li>RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock </li>
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</ul>
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</td></tr>
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<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void RCC_AHB1PeriphClockLPModeCmd </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_AHB1Periph</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. </p>
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<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
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<dd>
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After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
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<dd>
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By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB1 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
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<li>RCC_AHB1Periph_GPIOA: GPIOA clock </li>
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<li>RCC_AHB1Periph_GPIOB: GPIOB clock </li>
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<li>RCC_AHB1Periph_GPIOC: GPIOC clock </li>
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<li>RCC_AHB1Periph_GPIOD: GPIOD clock </li>
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<li>RCC_AHB1Periph_GPIOE: GPIOE clock </li>
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<li>RCC_AHB1Periph_GPIOF: GPIOF clock </li>
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<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
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<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
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<li>RCC_AHB1Periph_GPIOI: GPIOI clock </li>
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|
<li>RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) </li>
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<li>RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) </li>
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<li>RCC_AHB1Periph_CRC: CRC clock </li>
|
|
<li>RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock </li>
|
|
<li>RCC_AHB1Periph_DMA1: DMA1 clock </li>
|
|
<li>RCC_AHB1Periph_DMA2: DMA2 clock </li>
|
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<li>RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) </li>
|
|
<li>RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock </li>
|
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<li>RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock </li>
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<li>RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock </li>
|
|
<li>RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock </li>
|
|
<li>RCC_AHB1Periph_OTG_HS: USB OTG HS clock </li>
|
|
<li>RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
|
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</dd>
|
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</dl>
|
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<dl class="retval"><dt>Return values</dt><dd>
|
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<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
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</dd>
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</dl>
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</div>
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<tr>
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<td class="memname">void RCC_AHB1PeriphResetCmd </td>
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<td>(</td>
|
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<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB1Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
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<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Forces or releases AHB1 peripheral reset. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHB1Periph</td><td>specifies the AHB1 peripheral to reset. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_AHB1Periph_GPIOA: GPIOA clock </li>
|
|
<li>RCC_AHB1Periph_GPIOB: GPIOB clock </li>
|
|
<li>RCC_AHB1Periph_GPIOC: GPIOC clock </li>
|
|
<li>RCC_AHB1Periph_GPIOD: GPIOD clock </li>
|
|
<li>RCC_AHB1Periph_GPIOE: GPIOE clock </li>
|
|
<li>RCC_AHB1Periph_GPIOF: GPIOF clock </li>
|
|
<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
|
|
<li>RCC_AHB1Periph_GPIOG: GPIOG clock </li>
|
|
<li>RCC_AHB1Periph_GPIOI: GPIOI clock </li>
|
|
<li>RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) </li>
|
|
<li>RCC_AHB1Periph_CRC: CRC clock </li>
|
|
<li>RCC_AHB1Periph_DMA1: DMA1 clock </li>
|
|
<li>RCC_AHB1Periph_DMA2: DMA2 clock </li>
|
|
<li>RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) </li>
|
|
<li>RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock </li>
|
|
<li>RCC_AHB1Periph_OTG_HS: USB OTG HS clock</li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void RCC_AHB2PeriphClockCmd </td>
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<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB2Periph</em>, </td>
|
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</tr>
|
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<tr>
|
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Enables or disables the AHB2 peripheral clock. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_AHB2Periph_DCMI: DCMI clock </li>
|
|
<li>RCC_AHB2Periph_CRYP: CRYP clock </li>
|
|
<li>RCC_AHB2Periph_HASH: HASH clock </li>
|
|
<li>RCC_AHB2Periph_RNG: RNG clock </li>
|
|
<li>RCC_AHB2Periph_OTG_FS: USB OTG FS clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void RCC_AHB2PeriphClockLPModeCmd </td>
|
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<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>RCC_AHB2Periph</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
|
|
<dd>
|
|
After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
|
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<dd>
|
|
By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB2 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_AHB2Periph_DCMI: DCMI clock </li>
|
|
<li>RCC_AHB2Periph_CRYP: CRYP clock </li>
|
|
<li>RCC_AHB2Periph_HASH: HASH clock </li>
|
|
<li>RCC_AHB2Periph_RNG: RNG clock </li>
|
|
<li>RCC_AHB2Periph_OTG_FS: USB OTG FS clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
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</dd>
|
|
</dl>
|
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<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
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<tr><td class="paramname">None</td><td></td></tr>
|
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</table>
|
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gafb119d6d1955d1b8c361e8140845ac5a"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
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<td class="memname">void RCC_AHB2PeriphResetCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB2Periph</em>, </td>
|
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</tr>
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<tr>
|
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Forces or releases AHB2 peripheral reset. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHB2Periph</td><td>specifies the AHB2 peripheral to reset. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_AHB2Periph_DCMI: DCMI clock </li>
|
|
<li>RCC_AHB2Periph_CRYP: CRYP clock </li>
|
|
<li>RCC_AHB2Periph_HASH: HASH clock </li>
|
|
<li>RCC_AHB2Periph_RNG: RNG clock </li>
|
|
<li>RCC_AHB2Periph_OTG_FS: USB OTG FS clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
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</dd>
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</dl>
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<p><div class="dynheader">
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Here is the caller graph for this function:</div>
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<div class="dyncontent">
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<div class="center"><img src="group___r_c_c_gafb119d6d1955d1b8c361e8140845ac5a_icgraph.png" border="0" usemap="#group___r_c_c_gafb119d6d1955d1b8c361e8140845ac5a_icgraph" alt=""/></div>
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<map name="group___r_c_c_gafb119d6d1955d1b8c361e8140845ac5a_icgraph" id="group___r_c_c_gafb119d6d1955d1b8c361e8140845ac5a_icgraph">
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<area shape="rect" id="node2" href="group___c_r_y_p___group1.html#gae19e54c9910b697e38f6c7577704ffae" title="Deinitializes the CRYP peripheral registers to their default reset values. " alt="" coords="241,31,340,57"/><area shape="rect" id="node3" href="group___h_a_s_h___group1.html#ga88717fe3a4f557182841a958e1dcd9c7" title="De-initializes the HASH peripheral registers to their default reset values. " alt="" coords="241,81,340,108"/><area shape="rect" id="node8" href="group___r_n_g___group1.html#ga15ff5e649080076eebd51143b9ac4491" title="De-initializes the RNG peripheral registers to their default reset values. " alt="" coords="245,132,336,159"/><area shape="rect" id="node4" href="group___h_a_s_h___group7.html#ga82a155884e458cc6b7c1a4565c1ac8e9" title="Compute the HASH MD5 digest. " alt="" coords="393,5,485,32"/><area shape="rect" id="node5" href="group___h_a_s_h___group7.html#gac61733e7aa66bdd2f21be4b34165b5be" title="Compute the HMAC MD5 digest. " alt="" coords="391,56,486,83"/><area shape="rect" id="node6" href="group___h_a_s_h___group6.html#ga2728c02c36de6d800e1ede56ea7789cb" title="Compute the HASH SHA1 digest. " alt="" coords="389,107,488,133"/><area shape="rect" id="node7" href="group___h_a_s_h___group6.html#ga2e38e900ca7838c1cea17cef19953a5e" title="Compute the HMAC SHA1 digest. " alt="" coords="388,157,489,184"/></map>
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</div>
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</p>
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</div>
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</div>
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<a class="anchor" id="ga4eb8c119f2e9bf2bd2e042d27f151338"></a>
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<div class="memitem">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_AHB3PeriphClockCmd </td>
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<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>RCC_AHB3Periph</em>, </td>
|
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</tr>
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<tr>
|
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
|
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the AHB3 peripheral clock. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) </td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
|
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</div>
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</div>
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<a class="anchor" id="ga4e1df07cdfd81c068902d9d35fcc3911"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_AHB3PeriphClockLPModeCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB3Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
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<tr>
|
|
<td></td>
|
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
|
|
|
|
<p>Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
|
|
<dd>
|
|
After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
|
|
<dd>
|
|
By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHBPeriph</td><td>specifies the AHB3 peripheral to gates its clock. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices) </td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
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<a class="anchor" id="gaee44f159a1ca9ebdd7117bff387cd592"></a>
|
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<div class="memitem">
|
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<div class="memproto">
|
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_AHB3PeriphResetCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_AHB3Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
|
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<td></td><td></td>
|
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</tr>
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</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Forces or releases AHB3 peripheral reset. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_AHB3Periph</td><td>specifies the AHB3 peripheral to reset. This parameter must be: RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) </td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
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</div>
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</div>
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<a class="anchor" id="gaee7cc5d73af7fe1986fceff8afd3973e"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
|
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<tr>
|
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<td class="memname">void RCC_APB1PeriphClockCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_APB1Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
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<tr>
|
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the Low Speed APB (APB1) peripheral clock. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB1Periph</td><td>specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB1Periph_TIM2: TIM2 clock </li>
|
|
<li>RCC_APB1Periph_TIM3: TIM3 clock </li>
|
|
<li>RCC_APB1Periph_TIM4: TIM4 clock </li>
|
|
<li>RCC_APB1Periph_TIM5: TIM5 clock </li>
|
|
<li>RCC_APB1Periph_TIM6: TIM6 clock </li>
|
|
<li>RCC_APB1Periph_TIM7: TIM7 clock </li>
|
|
<li>RCC_APB1Periph_TIM12: TIM12 clock </li>
|
|
<li>RCC_APB1Periph_TIM13: TIM13 clock </li>
|
|
<li>RCC_APB1Periph_TIM14: TIM14 clock </li>
|
|
<li>RCC_APB1Periph_WWDG: WWDG clock </li>
|
|
<li>RCC_APB1Periph_SPI2: SPI2 clock </li>
|
|
<li>RCC_APB1Periph_SPI3: SPI3 clock </li>
|
|
<li>RCC_APB1Periph_USART2: USART2 clock </li>
|
|
<li>RCC_APB1Periph_USART3: USART3 clock </li>
|
|
<li>RCC_APB1Periph_UART4: UART4 clock </li>
|
|
<li>RCC_APB1Periph_UART5: UART5 clock </li>
|
|
<li>RCC_APB1Periph_I2C1: I2C1 clock </li>
|
|
<li>RCC_APB1Periph_I2C2: I2C2 clock </li>
|
|
<li>RCC_APB1Periph_I2C3: I2C3 clock </li>
|
|
<li>RCC_APB1Periph_CAN1: CAN1 clock </li>
|
|
<li>RCC_APB1Periph_CAN2: CAN2 clock </li>
|
|
<li>RCC_APB1Periph_PWR: PWR clock </li>
|
|
<li>RCC_APB1Periph_DAC: DAC clock </li>
|
|
<li>RCC_APB1Periph_UART7: UART7 clock </li>
|
|
<li>RCC_APB1Periph_UART8: UART8 clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
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<a class="anchor" id="ga84dd64badb84768cbcf19e241cadff50"></a>
|
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<div class="memitem">
|
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<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_APB1PeriphClockLPModeCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_APB1Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
|
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<td></td><td></td>
|
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</tr>
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</table>
|
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</div><div class="memdoc">
|
|
|
|
<p>Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
|
|
<dd>
|
|
After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
|
|
<dd>
|
|
By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB1Periph</td><td>specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB1Periph_TIM2: TIM2 clock </li>
|
|
<li>RCC_APB1Periph_TIM3: TIM3 clock </li>
|
|
<li>RCC_APB1Periph_TIM4: TIM4 clock </li>
|
|
<li>RCC_APB1Periph_TIM5: TIM5 clock </li>
|
|
<li>RCC_APB1Periph_TIM6: TIM6 clock </li>
|
|
<li>RCC_APB1Periph_TIM7: TIM7 clock </li>
|
|
<li>RCC_APB1Periph_TIM12: TIM12 clock </li>
|
|
<li>RCC_APB1Periph_TIM13: TIM13 clock </li>
|
|
<li>RCC_APB1Periph_TIM14: TIM14 clock </li>
|
|
<li>RCC_APB1Periph_WWDG: WWDG clock </li>
|
|
<li>RCC_APB1Periph_SPI2: SPI2 clock </li>
|
|
<li>RCC_APB1Periph_SPI3: SPI3 clock </li>
|
|
<li>RCC_APB1Periph_USART2: USART2 clock </li>
|
|
<li>RCC_APB1Periph_USART3: USART3 clock </li>
|
|
<li>RCC_APB1Periph_UART4: UART4 clock </li>
|
|
<li>RCC_APB1Periph_UART5: UART5 clock </li>
|
|
<li>RCC_APB1Periph_I2C1: I2C1 clock </li>
|
|
<li>RCC_APB1Periph_I2C2: I2C2 clock </li>
|
|
<li>RCC_APB1Periph_I2C3: I2C3 clock </li>
|
|
<li>RCC_APB1Periph_CAN1: CAN1 clock </li>
|
|
<li>RCC_APB1Periph_CAN2: CAN2 clock </li>
|
|
<li>RCC_APB1Periph_PWR: PWR clock </li>
|
|
<li>RCC_APB1Periph_DAC: DAC clock </li>
|
|
<li>RCC_APB1Periph_UART7: UART7 clock </li>
|
|
<li>RCC_APB1Periph_UART8: UART8 clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
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<a class="anchor" id="gab197ae4369c10b92640a733b40ed2801"></a>
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<div class="memitem">
|
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<div class="memproto">
|
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_APB1PeriphResetCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_APB1Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Forces or releases Low Speed APB (APB1) peripheral reset. </p>
|
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB1Periph</td><td>specifies the APB1 peripheral to reset. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB1Periph_TIM2: TIM2 clock </li>
|
|
<li>RCC_APB1Periph_TIM3: TIM3 clock </li>
|
|
<li>RCC_APB1Periph_TIM4: TIM4 clock </li>
|
|
<li>RCC_APB1Periph_TIM5: TIM5 clock </li>
|
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<li>RCC_APB1Periph_TIM6: TIM6 clock </li>
|
|
<li>RCC_APB1Periph_TIM7: TIM7 clock </li>
|
|
<li>RCC_APB1Periph_TIM12: TIM12 clock </li>
|
|
<li>RCC_APB1Periph_TIM13: TIM13 clock </li>
|
|
<li>RCC_APB1Periph_TIM14: TIM14 clock </li>
|
|
<li>RCC_APB1Periph_WWDG: WWDG clock </li>
|
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<li>RCC_APB1Periph_SPI2: SPI2 clock </li>
|
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<li>RCC_APB1Periph_SPI3: SPI3 clock </li>
|
|
<li>RCC_APB1Periph_USART2: USART2 clock </li>
|
|
<li>RCC_APB1Periph_USART3: USART3 clock </li>
|
|
<li>RCC_APB1Periph_UART4: UART4 clock </li>
|
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<li>RCC_APB1Periph_UART5: UART5 clock </li>
|
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<li>RCC_APB1Periph_I2C1: I2C1 clock </li>
|
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<li>RCC_APB1Periph_I2C2: I2C2 clock </li>
|
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<li>RCC_APB1Periph_I2C3: I2C3 clock </li>
|
|
<li>RCC_APB1Periph_CAN1: CAN1 clock </li>
|
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<li>RCC_APB1Periph_CAN2: CAN2 clock </li>
|
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<li>RCC_APB1Periph_PWR: PWR clock </li>
|
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<li>RCC_APB1Periph_DAC: DAC clock </li>
|
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<li>RCC_APB1Periph_UART7: UART7 clock </li>
|
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<li>RCC_APB1Periph_UART8: UART8 clock </li>
|
|
</ul>
|
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</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
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</dd>
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</dl>
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<area shape="rect" id="node2" href="group___c_a_n___group1.html#ga002b74cd69574a14b17ad445090245cd" title="Deinitializes the CAN peripheral registers to their default reset values. " alt="" coords="251,5,341,32"/><area shape="rect" id="node3" href="group___d_a_c___group1.html#ga1fae225204e1e049d6795319e99ba8bc" title="Deinitializes the DAC peripheral registers to their default reset values. " alt="" coords="251,56,341,83"/><area shape="rect" id="node4" href="group___i2_c___group1.html#ga2ee214364603059ad5d9089f749f5bfd" title="Deinitialize the I2Cx peripheral registers to their default reset values. " alt="" coords="255,107,337,133"/><area shape="rect" id="node5" href="group___p_w_r___group1.html#gad03a0aac7bc3bc3a9fd012f3769a6990" title="Deinitializes the PWR peripheral registers to their default reset values. " alt="" coords="249,157,343,184"/><area shape="rect" id="node6" href="group___s_p_i___group1.html#gabe36880945fa56785283a9c0092124cc" title="De-initialize the SPIx peripheral registers to their default reset values. " alt="" coords="241,208,351,235"/><area shape="rect" id="node7" href="group___t_i_m___group1.html#ga1659cc0ce503ac151568e0c7c02b1ba5" title="Deinitializes the TIMx peripheral registers to their default reset values. " alt="" coords="255,259,337,285"/><area shape="rect" id="node8" href="group___u_s_a_r_t___group1.html#ga2f8e1ce72da21b6539d8e1f299ec3b0d" title="Deinitializes the USARTx peripheral registers to their default reset values. " alt="" coords="243,309,349,336"/><area shape="rect" id="node9" href="group___w_w_d_g___group1.html#ga7130f4dc861b9234b62e73f9f57f89a1" title="Deinitializes the WWDG peripheral registers to their default reset values. " alt="" coords="243,360,349,387"/></map>
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</p>
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<a class="anchor" id="ga56ff55caf8d835351916b40dd030bc87"></a>
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<tr>
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<td class="memname">void RCC_APB2PeriphClockCmd </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_APB2Periph</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
|
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the High Speed APB (APB2) peripheral clock. </p>
|
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<dl class="section note"><dt>Note</dt><dd>After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it. </dd></dl>
|
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB2Periph</td><td>specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB2Periph_TIM1: TIM1 clock </li>
|
|
<li>RCC_APB2Periph_TIM8: TIM8 clock </li>
|
|
<li>RCC_APB2Periph_USART1: USART1 clock </li>
|
|
<li>RCC_APB2Periph_USART6: USART6 clock </li>
|
|
<li>RCC_APB2Periph_ADC1: ADC1 clock </li>
|
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<li>RCC_APB2Periph_ADC2: ADC2 clock </li>
|
|
<li>RCC_APB2Periph_ADC3: ADC3 clock </li>
|
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<li>RCC_APB2Periph_SDIO: SDIO clock </li>
|
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<li>RCC_APB2Periph_SPI1: SPI1 clock </li>
|
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<li>RCC_APB2Periph_SPI4: SPI4 clock </li>
|
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<li>RCC_APB2Periph_SYSCFG: SYSCFG clock </li>
|
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<li>RCC_APB2Periph_TIM9: TIM9 clock </li>
|
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<li>RCC_APB2Periph_TIM10: TIM10 clock </li>
|
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<li>RCC_APB2Periph_TIM11: TIM11 clock </li>
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<li>RCC_APB2Periph_SPI5: SPI5 clock </li>
|
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<li>RCC_APB2Periph_SPI6: SPI6 clock </li>
|
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<li>RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
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|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<map name="group___r_c_c_ga56ff55caf8d835351916b40dd030bc87_icgraph" id="group___r_c_c_ga56ff55caf8d835351916b40dd030bc87_icgraph">
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<td class="memname">void RCC_APB2PeriphClockLPModeCmd </td>
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<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_APB2Periph</em>, </td>
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</tr>
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<tr>
|
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>Peripheral clock gating in SLEEP mode can be used to further reduce power consumption. </dd>
|
|
<dd>
|
|
After wakeup from SLEEP mode, the peripheral clock is enabled again. </dd>
|
|
<dd>
|
|
By default, all peripheral clocks are enabled during SLEEP mode. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB2Periph</td><td>specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB2Periph_TIM1: TIM1 clock </li>
|
|
<li>RCC_APB2Periph_TIM8: TIM8 clock </li>
|
|
<li>RCC_APB2Periph_USART1: USART1 clock </li>
|
|
<li>RCC_APB2Periph_USART6: USART6 clock </li>
|
|
<li>RCC_APB2Periph_ADC1: ADC1 clock </li>
|
|
<li>RCC_APB2Periph_ADC2: ADC2 clock </li>
|
|
<li>RCC_APB2Periph_ADC3: ADC3 clock </li>
|
|
<li>RCC_APB2Periph_SDIO: SDIO clock </li>
|
|
<li>RCC_APB2Periph_SPI1: SPI1 clock </li>
|
|
<li>RCC_APB2Periph_SPI4: SPI4 clock </li>
|
|
<li>RCC_APB2Periph_SYSCFG: SYSCFG clock </li>
|
|
<li>RCC_APB2Periph_TIM9: TIM9 clock </li>
|
|
<li>RCC_APB2Periph_TIM10: TIM10 clock </li>
|
|
<li>RCC_APB2Periph_TIM11: TIM11 clock </li>
|
|
<li>RCC_APB2Periph_SPI5: SPI5 clock </li>
|
|
<li>RCC_APB2Periph_SPI6: SPI6 clock </li>
|
|
<li>RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
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</dl>
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</div>
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<a class="anchor" id="gad94553850ac07106a27ee85fec37efdf"></a>
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<tr>
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<td class="memname">void RCC_APB2PeriphResetCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_APB2Periph</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td>)</td>
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|
<td></td><td></td>
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|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Forces or releases High Speed APB (APB2) peripheral reset. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_APB2Periph</td><td>specifies the APB2 peripheral to reset. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_APB2Periph_TIM1: TIM1 clock </li>
|
|
<li>RCC_APB2Periph_TIM8: TIM8 clock </li>
|
|
<li>RCC_APB2Periph_USART1: USART1 clock </li>
|
|
<li>RCC_APB2Periph_USART6: USART6 clock </li>
|
|
<li>RCC_APB2Periph_ADC1: ADC1 clock </li>
|
|
<li>RCC_APB2Periph_ADC2: ADC2 clock </li>
|
|
<li>RCC_APB2Periph_ADC3: ADC3 clock </li>
|
|
<li>RCC_APB2Periph_SDIO: SDIO clock </li>
|
|
<li>RCC_APB2Periph_SPI1: SPI1 clock </li>
|
|
<li>RCC_APB2Periph_SPI4: SPI4 clock </li>
|
|
<li>RCC_APB2Periph_SYSCFG: SYSCFG clock </li>
|
|
<li>RCC_APB2Periph_TIM9: TIM9 clock </li>
|
|
<li>RCC_APB2Periph_TIM10: TIM10 clock </li>
|
|
<li>RCC_APB2Periph_TIM11: TIM11 clock </li>
|
|
<li>RCC_APB2Periph_SPI5: SPI5 clock </li>
|
|
<li>RCC_APB2Periph_SPI6: SPI6 clock </li>
|
|
<li>RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
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</dl>
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<map name="group___r_c_c_gad94553850ac07106a27ee85fec37efdf_icgraph" id="group___r_c_c_gad94553850ac07106a27ee85fec37efdf_icgraph">
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<area shape="rect" id="node2" href="group___a_d_c___group1.html#ga1962afdd9eebe5c896bbba2e4f26fe09" title="Deinitializes all ADCs peripherals registers to their default reset values. " alt="" coords="255,5,344,32"/><area shape="rect" id="node3" href="group___l_t_d_c___group1.html#gad3522837b5ef2b99653e230e649fc149" title="Deinitializes the LTDC peripheral registers to their default reset values. " alt="" coords="253,56,346,83"/><area shape="rect" id="node4" href="group___s_a_i___group1.html#gadcef52be2d2792a70f67b6e7872b334e" title="Deinitialize the SAIx peripheral registers to their default reset values. " alt="" coords="258,107,341,133"/><area shape="rect" id="node5" href="group___s_d_i_o___group1.html#gac359d2c6c67a2590f8f9b720c0e4ff1b" title="Deinitializes the SDIO peripheral registers to their default reset values. " alt="" coords="253,157,346,184"/><area shape="rect" id="node6" href="group___s_p_i___group1.html#gabe36880945fa56785283a9c0092124cc" title="De-initialize the SPIx peripheral registers to their default reset values. " alt="" coords="245,208,354,235"/><area shape="rect" id="node7" href="group___s_y_s_c_f_g___private___functions.html#gaf2f9faa2df9a59a68ae17fae23bc478e" title="Deinitializes the Alternate Functions (remap and EXTI configuration) registers to their default reset..." alt="" coords="241,259,357,285"/><area shape="rect" id="node8" href="group___t_i_m___group1.html#ga1659cc0ce503ac151568e0c7c02b1ba5" title="Deinitializes the TIMx peripheral registers to their default reset values. " alt="" coords="258,309,341,336"/><area shape="rect" id="node9" href="group___u_s_a_r_t___group1.html#ga2f8e1ce72da21b6539d8e1f299ec3b0d" title="Deinitializes the USARTx peripheral registers to their default reset values. " alt="" coords="247,360,352,387"/></map>
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<td class="memname">void RCC_BackupResetCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em></td><td>)</td>
|
|
<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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|
|
<p>Forces or releases the Backup domain reset. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register. </dd>
|
|
<dd>
|
|
The BKPSRAM is not affected by this reset. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">NewState</td><td>new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
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</div>
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</div>
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<tr>
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<td class="memname">void RCC_ClearFlag </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<td class="paramname"></td><td>)</td>
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<td></td>
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</tr>
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</div><div class="memdoc">
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<p>Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<tr>
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<td class="memname">void RCC_ClearITPendingBit </td>
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<td>(</td>
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<td class="paramtype">uint8_t </td>
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<td class="paramname"><em>RCC_IT</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Clears the RCC's interrupt pending bits. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">RCC_IT</td><td>specifies the interrupt pending bit to clear. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_IT_LSIRDY: LSI ready interrupt </li>
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<li>RCC_IT_LSERDY: LSE ready interrupt </li>
|
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<li>RCC_IT_HSIRDY: HSI ready interrupt </li>
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<li>RCC_IT_HSERDY: HSE ready interrupt </li>
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<li>RCC_IT_PLLRDY: main PLL ready interrupt </li>
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<li>RCC_IT_PLLI2SRDY: PLLI2S ready interrupt </li>
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<li>RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) </li>
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<li>RCC_IT_CSS: Clock Security System interrupt </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void RCC_ClockSecuritySystemCmd </td>
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<td>(</td>
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<td class="paramtype">FunctionalState </td>
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<td class="paramname"><em>NewState</em></td><td>)</td>
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<td></td>
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</tr>
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</div><div class="memdoc">
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<p>Enables or disables the Clock Security System. </p>
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<dl class="section note"><dt>Note</dt><dd>If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">NewState</td><td>new state of the Clock Security System. This parameter can be: ENABLE or DISABLE. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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<td class="memname">void RCC_DeInit </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<td class="paramname"></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>Resets the RCC clock configuration to the default reset state. </p>
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<dl class="section note"><dt>Note</dt><dd>The default reset state of the clock configuration is given below:<ul>
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<li>HSI ON and used as system clock source</li>
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<li>HSE, PLL and PLLI2S OFF</li>
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<li>AHB, APB1 and APB2 prescaler set to 1.</li>
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<li>CSS, MCO1 and MCO2 OFF</li>
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<li>All interrupts disabled </li>
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</ul>
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</dd>
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<dd>
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This function doesn't modify the configuration of the<ul>
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<li>Peripheral clocks</li>
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|
<li>LSI, LSE and RTC clocks </li>
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</ul>
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</dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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<td class="memname">void RCC_GetClocksFreq </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="struct_r_c_c___clocks_type_def.html">RCC_ClocksTypeDef</a> * </td>
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<td class="paramname"><em>RCC_Clocks</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. </p>
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<dl class="section note"><dt>Note</dt><dd>The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source: </dd>
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<dd>
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If SYSCLK source is HSI, function returns values based on <a class="el" href="group___library__configuration__section.html#gaaa8c76e274d0f6dd2cefb5d0b17fbc37">HSI_VALUE(*)</a> </dd>
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<dd>
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If SYSCLK source is HSE, function returns values based on <a class="el" href="group___library__configuration__section.html#gaeafcff4f57440c60e64812dddd13e7cb" title="In the following line adjust the value of External High Speed oscillator (HSE) used in your applicati...">HSE_VALUE(**)</a> </dd>
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<dd>
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If SYSCLK source is PLL, function returns values based on <a class="el" href="group___library__configuration__section.html#gaeafcff4f57440c60e64812dddd13e7cb" title="In the following line adjust the value of External High Speed oscillator (HSE) used in your applicati...">HSE_VALUE(**)</a> or <a class="el" href="group___library__configuration__section.html#gaaa8c76e274d0f6dd2cefb5d0b17fbc37">HSI_VALUE(*)</a> multiplied/divided by the PLL factors. </dd>
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<dd>
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(*) HSI_VALUE is a constant defined in <a class="el" href="stm32f4xx_8h.html" title="CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...">stm32f4xx.h</a> file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature. </dd>
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<dd>
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(**) HSE_VALUE is a constant defined in <a class="el" href="stm32f4xx_8h.html" title="CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...">stm32f4xx.h</a> file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.</dd>
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<dd>
|
|
The result of this function could be not correct when using fractional value for HSE crystal.</dd></dl>
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|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
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|
<tr><td class="paramname">RCC_Clocks</td><td>pointer to a <a class="el" href="struct_r_c_c___clocks_type_def.html">RCC_ClocksTypeDef</a> structure which will hold the clocks frequencies.</td></tr>
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|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters. </dd>
|
|
<dd>
|
|
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.</dd></dl>
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|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">FlagStatus RCC_GetFlagStatus </td>
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<td>(</td>
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<td class="paramtype">uint8_t </td>
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<td class="paramname"><em>RCC_FLAG</em></td><td>)</td>
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<p>Checks whether the specified RCC flag is set or not. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
|
|
<tr><td class="paramname">RCC_FLAG</td><td>specifies the flag to check. This parameter can be one of the following values: <ul>
|
|
<li>RCC_FLAG_HSIRDY: HSI oscillator clock ready </li>
|
|
<li>RCC_FLAG_HSERDY: HSE oscillator clock ready </li>
|
|
<li>RCC_FLAG_PLLRDY: main PLL clock ready </li>
|
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<li>RCC_FLAG_PLLI2SRDY: PLLI2S clock ready </li>
|
|
<li>RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_FLAG_LSERDY: LSE oscillator clock ready </li>
|
|
<li>RCC_FLAG_LSIRDY: LSI oscillator clock ready </li>
|
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<li>RCC_FLAG_BORRST: POR/PDR or BOR reset </li>
|
|
<li>RCC_FLAG_PINRST: Pin reset </li>
|
|
<li>RCC_FLAG_PORRST: POR/PDR reset </li>
|
|
<li>RCC_FLAG_SFTRST: Software reset </li>
|
|
<li>RCC_FLAG_IWDGRST: Independent Watchdog reset </li>
|
|
<li>RCC_FLAG_WWDGRST: Window Watchdog reset </li>
|
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<li>RCC_FLAG_LPWRRST: Low Power reset </li>
|
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">The</td><td>new state of RCC_FLAG (SET or RESET). </td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">ITStatus RCC_GetITStatus </td>
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<td>(</td>
|
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<td class="paramtype">uint8_t </td>
|
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<td class="paramname"><em>RCC_IT</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>Checks whether the specified RCC interrupt has occurred or not. </p>
|
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_IT</td><td>specifies the RCC interrupt source to check. This parameter can be one of the following values: <ul>
|
|
<li>RCC_IT_LSIRDY: LSI ready interrupt </li>
|
|
<li>RCC_IT_LSERDY: LSE ready interrupt </li>
|
|
<li>RCC_IT_HSIRDY: HSI ready interrupt </li>
|
|
<li>RCC_IT_HSERDY: HSE ready interrupt </li>
|
|
<li>RCC_IT_PLLRDY: main PLL ready interrupt </li>
|
|
<li>RCC_IT_PLLI2SRDY: PLLI2S ready interrupt </li>
|
|
<li>RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices) </li>
|
|
<li>RCC_IT_CSS: Clock Security System interrupt </li>
|
|
</ul>
|
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</td></tr>
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|
</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">The</td><td>new state of RCC_IT (SET or RESET). </td></tr>
|
|
</table>
|
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</dd>
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</dl>
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</div>
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<td class="memname">uint8_t RCC_GetSYSCLKSource </td>
|
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<td>(</td>
|
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<td class="paramtype">void </td>
|
|
<td class="paramname"></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<p>Returns the clock source used as system clock. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">The</td><td>clock source used as system clock. The returned value can be one of the following:<ul>
|
|
<li>0x00: HSI used as system clock</li>
|
|
<li>0x04: HSE used as system clock</li>
|
|
<li>0x08: PLL used as system clock </li>
|
|
</ul>
|
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</td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void RCC_HCLKConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_SYSCLK</em></td><td>)</td>
|
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the AHB clock (HCLK). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>Depending on the device voltage range, the software has to set correctly these bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions") </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_SYSCLK</td><td>defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values: <ul>
|
|
<li>RCC_SYSCLK_Div1: AHB clock = SYSCLK </li>
|
|
<li>RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 </li>
|
|
<li>RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 </li>
|
|
<li>RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 </li>
|
|
<li>RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 </li>
|
|
<li>RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 </li>
|
|
<li>RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 </li>
|
|
<li>RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 </li>
|
|
<li>RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
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</dl>
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</div>
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<td class="memname">void RCC_HSEConfig </td>
|
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<td>(</td>
|
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<td class="paramtype">uint8_t </td>
|
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<td class="paramname"><em>RCC_HSE</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the External High Speed oscillator (HSE). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock. </dd>
|
|
<dd>
|
|
HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it). </dd>
|
|
<dd>
|
|
The HSE is stopped by hardware when entering STOP and STANDBY modes. </dd>
|
|
<dd>
|
|
This function reset the CSSON bit, so if the Clock security system(CSS) was previously enabled you have to enable it again after calling this function. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_HSE</td><td>specifies the new state of the HSE. This parameter can be one of the following values: <ul>
|
|
<li>RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles. </li>
|
|
<li>RCC_HSE_ON: turn ON the HSE oscillator </li>
|
|
<li>RCC_HSE_Bypass: HSE oscillator bypassed with external clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
|
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|
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</div>
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</div>
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<a class="anchor" id="ga0c6772a1e43765909495f57815ef69e2"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
|
<td class="memname">void RCC_HSICmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or disables the Internal High Speed oscillator (HSI). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled). </dd>
|
|
<dd>
|
|
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI. </dd>
|
|
<dd>
|
|
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">NewState</td><td>new state of the HSI. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles. </dd></dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
|
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</div>
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</div>
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<a class="anchor" id="ga6c56f8529988fcc8f4dbffbc1bab27d0"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
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<td class="memname">void RCC_I2SCLKConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_I2SCLKSource</em></td><td>)</td>
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<td></td>
|
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</tr>
|
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</table>
|
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</div><div class="memdoc">
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<p>Configures the I2S clock source (I2SCLK). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function must be called before enabling the I2S APB clock. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_I2SCLKSource</td><td>specifies the I2S clock source. This parameter can be one of the following values: <ul>
|
|
<li>RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source </li>
|
|
<li>RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin used as I2S clock source </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
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</div>
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</div>
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<a class="anchor" id="gaa953aa226e9ce45300d535941e4dfe2f"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
|
<td class="memname">void RCC_ITConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint8_t </td>
|
|
<td class="paramname"><em>RCC_IT</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
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<td>)</td>
|
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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|
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<p>Enables or disables the specified RCC interrupts. </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_IT</td><td>specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values: <ul>
|
|
<li>RCC_IT_LSIRDY: LSI ready interrupt </li>
|
|
<li>RCC_IT_LSERDY: LSE ready interrupt </li>
|
|
<li>RCC_IT_HSIRDY: HSI ready interrupt </li>
|
|
<li>RCC_IT_HSERDY: HSE ready interrupt </li>
|
|
<li>RCC_IT_PLLRDY: main PLL ready interrupt </li>
|
|
<li>RCC_IT_PLLI2SRDY: PLLI2S ready interrupt </li>
|
|
<li>RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">NewState</td><td>new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
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|
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</div>
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</div>
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<a class="anchor" id="ga65209ab5c3589b249c7d70f978735ca6"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
|
|
<td class="memname">void RCC_LSEConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint8_t </td>
|
|
<td class="paramname"><em>RCC_LSE</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
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|
|
<p>Configures the External Low Speed oscillator (LSE). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset). </dd>
|
|
<dd>
|
|
After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_LSE</td><td>specifies the new state of the LSE. This parameter can be one of the following values: <ul>
|
|
<li>RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles. </li>
|
|
<li>RCC_LSE_ON: turn ON the LSE oscillator </li>
|
|
<li>RCC_LSE_Bypass: LSE oscillator bypassed with external clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
|
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<a class="anchor" id="ga1337eb44ba2fce5b3e8ccd92cd01bde4"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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|
<tr>
|
|
<td class="memname">void RCC_LSEModeConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint8_t </td>
|
|
<td class="paramname"><em>Mode</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Configures the External Low Speed oscillator mode (LSE mode). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This mode is only available for STM32F411xx devices. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">Mode</td><td>specifies the LSE mode. This parameter can be one of the following values: <ul>
|
|
<li>RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode. </li>
|
|
<li>RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode. </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
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<a class="anchor" id="ga81e3ca29fd154ac2019bba6936d6d5ed"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_LSICmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Enables or disables the Internal Low Speed oscillator (LSI). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC. </dd>
|
|
<dd>
|
|
LSI can not be disabled if the IWDG is running. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">NewState</td><td>new state of the LSI. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles. </dd></dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
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<a class="anchor" id="gac04a91996aefd2a517cf90c2a44830d2"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_LTDCCLKDivConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_PLLSAIDivR</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Configures the LTDC clock Divider coming from PLLSAI. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>The LTDC peripheral is only available with STM32F429xx/439xx Devices.</dd>
|
|
<dd>
|
|
This function must be called before enabling the PLLSAI.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_PLLSAIDivR</td><td>specifies the PLLSAI division factor for LTDC clock . This parameter must be a number between 2 and 16. LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
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<a class="anchor" id="ga15c9ecb6ef015ed008cb28e5b7a50531"></a>
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<div class="memitem">
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|
<div class="memproto">
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|
<table class="memname">
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|
<tr>
|
|
<td class="memname">void RCC_MCO1Config </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_MCO1Source</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_MCO1Div</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td>)</td>
|
|
<td></td><td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Selects the clock source to output on MCO1 pin(PA8). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>PA8 should be configured in alternate function mode. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_MCO1Source</td><td>specifies the clock source to output. This parameter can be one of the following values: <ul>
|
|
<li>RCC_MCO1Source_HSI: HSI clock selected as MCO1 source </li>
|
|
<li>RCC_MCO1Source_LSE: LSE clock selected as MCO1 source </li>
|
|
<li>RCC_MCO1Source_HSE: HSE clock selected as MCO1 source </li>
|
|
<li>RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">RCC_MCO1Div</td><td>specifies the MCO1 prescaler. This parameter can be one of the following values: <ul>
|
|
<li>RCC_MCO1Div_1: no division applied to MCO1 clock </li>
|
|
<li>RCC_MCO1Div_2: division by 2 applied to MCO1 clock </li>
|
|
<li>RCC_MCO1Div_3: division by 3 applied to MCO1 clock </li>
|
|
<li>RCC_MCO1Div_4: division by 4 applied to MCO1 clock </li>
|
|
<li>RCC_MCO1Div_5: division by 5 applied to MCO1 clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
|
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<a class="anchor" id="gaf50f10675b747de60c739e44e5c22aee"></a>
|
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<div class="memitem">
|
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<div class="memproto">
|
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_MCO2Config </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_MCO2Source</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_MCO2Div</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td>)</td>
|
|
<td></td><td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Selects the clock source to output on MCO2 pin(PC9). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>PC9 should be configured in alternate function mode. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_MCO2Source</td><td>specifies the clock source to output. This parameter can be one of the following values: <ul>
|
|
<li>RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source </li>
|
|
<li>RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source </li>
|
|
<li>RCC_MCO2Source_HSE: HSE clock selected as MCO2 source </li>
|
|
<li>RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source </li>
|
|
</ul>
|
|
</td></tr>
|
|
<tr><td class="paramname">RCC_MCO2Div</td><td>specifies the MCO2 prescaler. This parameter can be one of the following values: <ul>
|
|
<li>RCC_MCO2Div_1: no division applied to MCO2 clock </li>
|
|
<li>RCC_MCO2Div_2: division by 2 applied to MCO2 clock </li>
|
|
<li>RCC_MCO2Div_3: division by 3 applied to MCO2 clock </li>
|
|
<li>RCC_MCO2Div_4: division by 4 applied to MCO2 clock </li>
|
|
<li>RCC_MCO2Div_5: division by 5 applied to MCO2 clock </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
|
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<a class="anchor" id="ga448137346d4292985d4e7a61dd1a824f"></a>
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<div class="memitem">
|
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<div class="memproto">
|
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<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_PCLK1Config </td>
|
|
<td>(</td>
|
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<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>RCC_HCLK</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the Low Speed APB clock (PCLK1). </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_HCLK</td><td>defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values: <ul>
|
|
<li>RCC_HCLK_Div1: APB1 clock = HCLK </li>
|
|
<li>RCC_HCLK_Div2: APB1 clock = HCLK/2 </li>
|
|
<li>RCC_HCLK_Div4: APB1 clock = HCLK/4 </li>
|
|
<li>RCC_HCLK_Div8: APB1 clock = HCLK/8 </li>
|
|
<li>RCC_HCLK_Div16: APB1 clock = HCLK/16 </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
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</dd>
|
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</dl>
|
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</div>
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</div>
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<a class="anchor" id="ga09f9c010a4adca9e036da42c2ca6126a"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_PCLK2Config </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_HCLK</em></td><td>)</td>
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<td></td>
|
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</tr>
|
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</table>
|
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</div><div class="memdoc">
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<p>Configures the High Speed APB clock (PCLK2). </p>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_HCLK</td><td>defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values: <ul>
|
|
<li>RCC_HCLK_Div1: APB2 clock = HCLK </li>
|
|
<li>RCC_HCLK_Div2: APB2 clock = HCLK/2 </li>
|
|
<li>RCC_HCLK_Div4: APB2 clock = HCLK/4 </li>
|
|
<li>RCC_HCLK_Div8: APB2 clock = HCLK/8 </li>
|
|
<li>RCC_HCLK_Div16: APB2 clock = HCLK/16 </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
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</div>
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</div>
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<a class="anchor" id="ga84dee53c75e58fdb53571716593c2272"></a>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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|
<td class="memname">void RCC_PLLCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em></td><td>)</td>
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<td></td>
|
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</tr>
|
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</table>
|
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</div><div class="memdoc">
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<p>Enables or disables the main PLL. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source. </dd>
|
|
<dd>
|
|
The main PLL can not be disabled if it is used as system clock source </dd>
|
|
<dd>
|
|
The main PLL is disabled by hardware when entering STOP and STANDBY modes. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">NewState</td><td>new state of the main PLL. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
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</dl>
|
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</div>
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</div>
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<a class="anchor" id="ga154b93e90bfdede2a874244a1ff1002e"></a>
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">void RCC_PLLConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_PLLSource</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>PLLM</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>PLLN</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>PLLP</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>PLLQ</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td>)</td>
|
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<td></td><td></td>
|
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</tr>
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</table>
|
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</div><div class="memdoc">
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|
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<p>Configures the main PLL clock source, multiplication and division factors. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function must be used only when the main PLL is disabled.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_PLLSource</td><td>specifies the PLL entry clock source. This parameter can be one of the following values: <ul>
|
|
<li>RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry </li>
|
|
<li>RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry </li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">PLLM</td><td>specifies the division factor for PLL VCO input clock This parameter must be a number between 0 and 63. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">PLLN</td><td>specifies the multiplication factor for PLL VCO output clock This parameter must be a number between 192 and 432. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">PLLP</td><td>specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>You have to set the PLLP parameter correctly to not exceed 168 MHz on the System clock frequency.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">PLLQ</td><td>specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between 4 and 15. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.</dd></dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
|
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<a class="anchor" id="ga2efe493a6337d5e0034bfcdfb0f541e4"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_PLLI2SCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Enables or disables the PLLI2S. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">NewState</td><td>new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
|
|
<a class="anchor" id="gaf7b2c8f7533c8321dce97196d9f77fc1"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_PLLSAICmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Enables or disables the PLLSAI. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices</dd>
|
|
<dd>
|
|
The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">NewState</td><td>new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
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<a class="anchor" id="gaed7cbf4255d155c78a714a70752d14bf"></a>
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|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_PLLSAIConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>PLLSAIN</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>PLLSAIQ</em>, </td>
|
|
</tr>
|
|
<tr>
|
|
<td class="paramkey"></td>
|
|
<td></td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>PLLSAIR</em> </td>
|
|
</tr>
|
|
<tr>
|
|
<td></td>
|
|
<td>)</td>
|
|
<td></td><td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Configures the PLLSAI clock multiplication and division factors. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices</dd>
|
|
<dd>
|
|
This function must be used only when the PLLSAI is disabled. </dd>
|
|
<dd>
|
|
PLLSAI clock source is common with the main PLL (configured in RCC_PLLConfig function )</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">PLLSAIN</td><td>specifies the multiplication factor for PLLSAI VCO output clock This parameter must be a number between 192 and 432. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>You have to set the PLLSAIN parameter correctly to ensure that the VCO output frequency is between 192 and 432 MHz.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">PLLSAIQ</td><td>specifies the division factor for SAI1 clock This parameter must be a number between 2 and 15.</td></tr>
|
|
<tr><td class="paramname">PLLSAIR</td><td>specifies the division factor for LTDC clock This parameter must be a number between 2 and 7.</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
|
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<a class="anchor" id="ga9802f84846df2cea8e369234ed13b159"></a>
|
|
<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_RTCCLKCmd </td>
|
|
<td>(</td>
|
|
<td class="paramtype">FunctionalState </td>
|
|
<td class="paramname"><em>NewState</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Enables or disables the RTC clock. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">NewState</td><td>new state of the RTC clock. This parameter can be: ENABLE or DISABLE. </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
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</div>
|
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<a class="anchor" id="ga1473d8a5a020642966359611c44181b0"></a>
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<div class="memitem">
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|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_RTCCLKConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_RTCCLKSource</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Configures the RTC clock (RTCCLK). </p>
|
|
<dl class="section note"><dt>Note</dt><dd>As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset). </dd>
|
|
<dd>
|
|
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using <a class="el" href="group___r_c_c___group3.html#ga636c3b72f35391e67f12a551b15fa54a" title="Forces or releases the Backup domain reset. ">RCC_BackupResetCmd()</a> function, or by a Power On Reset (POR).</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_RTCCLKSource</td><td>specifies the RTC clock source. This parameter can be one of the following values: <ul>
|
|
<li>RCC_RTCCLKSource_LSE: LSE selected as RTC clock </li>
|
|
<li>RCC_RTCCLKSource_LSI: LSI selected as RTC clock </li>
|
|
<li>RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]</li>
|
|
</ul>
|
|
</td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="section note"><dt>Note</dt><dd>If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes. </dd>
|
|
<dd>
|
|
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).</dd></dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
</div>
|
|
</div>
|
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<a class="anchor" id="ga6cb4739d834adbf4009112357e1b1099"></a>
|
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<div class="memitem">
|
|
<div class="memproto">
|
|
<table class="memname">
|
|
<tr>
|
|
<td class="memname">void RCC_SAIBlockACLKConfig </td>
|
|
<td>(</td>
|
|
<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_SAIBlockACLKSource</em></td><td>)</td>
|
|
<td></td>
|
|
</tr>
|
|
</table>
|
|
</div><div class="memdoc">
|
|
|
|
<p>Configures SAI1BlockA clock source selection. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices.</dd>
|
|
<dd>
|
|
This function must be called before enabling PLLSAI, PLLI2S and the SAI clock. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_SAIBlockACLKSource</td><td>specifies the SAI <a class="el" href="struct_block.html">Block</a> A clock source. This parameter can be one of the following values: <ul>
|
|
<li>RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 <a class="el" href="struct_block.html">Block</a> A clock </li>
|
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<li>RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 <a class="el" href="struct_block.html">Block</a> A clock </li>
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<li>RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 <a class="el" href="struct_block.html">Block</a> A clock </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">void RCC_SAIBlockBCLKConfig </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_SAIBlockBCLKSource</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>Configures SAI1BlockB clock source selection. </p>
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<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices.</dd>
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<dd>
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This function must be called before enabling PLLSAI, PLLI2S and the SAI clock. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">RCC_SAIBlockBCLKSource</td><td>specifies the SAI <a class="el" href="struct_block.html">Block</a> B clock source. This parameter can be one of the following values: <ul>
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<li>RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 <a class="el" href="struct_block.html">Block</a> B clock </li>
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<li>RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 <a class="el" href="struct_block.html">Block</a> B clock </li>
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<li>RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin used as SAI1 <a class="el" href="struct_block.html">Block</a> B clock </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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<td class="memname">void RCC_SAIPLLI2SClkDivConfig </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_PLLI2SDivQ</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the SAI clock Divider coming from PLLI2S. </p>
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<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices.</dd>
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<dd>
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This function must be called before enabling the PLLI2S.</dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">RCC_PLLI2SDivQ</td><td>specifies the PLLI2S division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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</div>
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<a class="anchor" id="gabefc354915bd57804329349ec3f33fab"></a>
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<td class="memname">void RCC_SAIPLLSAIClkDivConfig </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_PLLSAIDivQ</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the SAI clock Divider coming from PLLSAI. </p>
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<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx devices.</dd>
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<dd>
|
|
This function must be called before enabling the PLLSAI.</dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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|
<table class="params">
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<tr><td class="paramname">RCC_PLLSAIDivQ</td><td>specifies the PLLSAI division factor for SAI1 clock . This parameter must be a number between 1 and 32. SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
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<table class="retval">
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<tr><td class="paramname">None</td><td></td></tr>
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</table>
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</dd>
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</dl>
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</div>
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<td class="memname">void RCC_SYSCLKConfig </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>RCC_SYSCLKSource</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the system clock (SYSCLK). </p>
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<dl class="section note"><dt>Note</dt><dd>The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled). </dd>
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<dd>
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A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use <a class="el" href="group___r_c_c___group2.html#gaaeb32311c208b2a980841c9c884a41ea" title="Returns the clock source used as system clock. ">RCC_GetSYSCLKSource()</a> function to know which clock is currently used as system clock source. </dd></dl>
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<dl class="params"><dt>Parameters</dt><dd>
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|
<table class="params">
|
|
<tr><td class="paramname">RCC_SYSCLKSource</td><td>specifies the clock source used as system clock. This parameter can be one of the following values: <ul>
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<li>RCC_SYSCLKSource_HSI: HSI selected as system clock source </li>
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<li>RCC_SYSCLKSource_HSE: HSE selected as system clock source </li>
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<li>RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source </li>
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</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
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</table>
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</dd>
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</dl>
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</div>
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<td class="memname">void RCC_TIMCLKPresConfig </td>
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<td>(</td>
|
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<td class="paramtype">uint32_t </td>
|
|
<td class="paramname"><em>RCC_TIMCLKPrescaler</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Configures the Timers clocks prescalers selection. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.</dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">RCC_TIMCLKPrescaler</td><td>: specifies the Timers clocks prescalers selection This parameter can be one of the following values: <ul>
|
|
<li>RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1 or 2, else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to division by 4 or more.</li>
|
|
</ul>
|
|
<ul>
|
|
<li>RCC_TIMPrescActivated: The Timers kernels clocks prescaler is equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding to division by 8 or more. </li>
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</ul>
|
|
</td></tr>
|
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</table>
|
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</dd>
|
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</dl>
|
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<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
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</table>
|
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</dd>
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</dl>
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</div>
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<td class="memname">ErrorStatus RCC_WaitForHSEStartUp </td>
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<td>(</td>
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<td class="paramtype">void </td>
|
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<td class="paramname"></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Waits for HSE start-up. </p>
|
|
<dl class="section note"><dt>Note</dt><dd>This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in <a class="el" href="stm32f4xx_8h.html" title="CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...">stm32f4xx.h</a> file. You can tailor it depending on the HSE crystal used in your application. </dd></dl>
|
|
<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramname">None</td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
<dl class="retval"><dt>Return values</dt><dd>
|
|
<table class="retval">
|
|
<tr><td class="paramname">An</td><td>ErrorStatus enumeration value:<ul>
|
|
<li>SUCCESS: HSE oscillator is stable and ready to use</li>
|
|
<li>ERROR: HSE oscillator not yet ready </li>
|
|
</ul>
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</td></tr>
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</table>
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</dd>
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</dl>
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<p><div class="dynheader">
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