97 lines
2.2 KiB
VHDL
97 lines
2.2 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project: YASG (Yet another signal generator)
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-- Project Page: https://github.com/id101010/vhdl-yasg/
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-- Authors: Aaron Schmocker & Timo Lang
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-- License: GPL v3
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-- Create Date: 15:38:41 05/17/2016
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----------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY spi_driver_tb IS
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END spi_driver_tb;
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ARCHITECTURE behavior OF spi_driver_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT spi_driver
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PORT(
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clk : IN std_logic;
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rst : IN std_logic;
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val : IN unsigned(11 downto 0);
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sck : OUT std_logic;
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cs : OUT std_logic;
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mosi : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal val : unsigned(11 downto 0) := (others => '0');
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--Outputs
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signal sck : std_logic;
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signal cs : std_logic;
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signal mosi : std_logic;
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-- Clock period definitions
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constant clk_period : time := 20 ns; --50mhz
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: spi_driver PORT MAP (
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clk => clk,
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rst => rst,
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val => val,
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sck => sck,
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cs => cs,
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mosi => mosi
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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rst <= '1';
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wait for 100 ns;
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rst <= '0';
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wait for clk_period*10;
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val <= to_unsigned(0,12);
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wait for clk_period*64;
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val <= to_unsigned(7,12);
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wait for clk_period*64;
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val <= to_unsigned(31,12);
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wait for clk_period*64;
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val <= to_unsigned(128,12);
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wait for clk_period*64;
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val <= to_unsigned(512,12);
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wait for clk_period*64;
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-- insert stimulus here
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wait;
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end process;
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END;
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