77 lines
3.1 KiB
VHDL
77 lines
3.1 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project: YASG (Yet another signal generator)
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-- Project Page: https://github.com/id101010/vhdl-yasg/
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-- Authors: Aaron Schmocker & Timo Lang
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-- License: GPL v3
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-- Create Date: 12:51:31 05/17/2016
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity spi_driver is
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Generic (clk_freq: natural:= 50000000; -- Clock-Frequency in Hz
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adc_res: natural:=12); -- Number of bits the DAC has
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Port ( clk : in STD_LOGIC; -- Clock input
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rst: in STD_LOGIC; -- High active, async reset
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val : in unsigned (adc_res-1 downto 0); -- DAC Value to write out
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sck : out STD_LOGIC; -- SPI SCK Signal (Clock)
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cs : out STD_LOGIC; -- SPI CS Signal (Chip Select)
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mosi : out STD_LOGIC); -- SPI MOSI Signal (Master Out Slave in)
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end spi_driver;
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architecture Behavioral of spi_driver is
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type states is(S_IDLE, S_WORK);
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signal state_reg, state_next: states := S_IDLE;
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signal counter_reg, counter_next: unsigned(5 downto 0) := (others => '0');
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signal shift_reg, shift_next: unsigned(19 downto 0):= (others => '0');
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begin
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REGS: process (clk, rst) is
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begin -- process start
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if rst = '1' then -- asynchronous reset (active high)
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state_reg <= S_IDLE;
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counter_reg <= to_unsigned(0,counter_reg'length);
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shift_reg <= to_unsigned(0,shift_reg'length);
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elsif rising_edge(clk) then -- rising clock edge
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state_reg <= state_next;
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counter_reg <= counter_next;
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shift_reg <= shift_next;
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end if;
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end process REGS;
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mosi <= shift_reg(shift_reg'high) when state_reg=S_WORK else '0';
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sck <= '1' when state_reg=S_WORK and counter_reg(0)='1' else '0';
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cs <= '1' when state_reg =S_IDLE else '0';
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NSL: process (state_reg, counter_reg, shift_reg, val) is
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begin
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state_next <= state_reg;
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counter_next <= counter_reg;
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shift_next <= shift_reg;
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case state_reg is -- switch on current state
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when S_IDLE => -- currently in idle state
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state_next <= S_WORK;
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counter_next <= to_unsigned(0,counter_reg'length);
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shift_next(19 downto 16) <= "0011"; --Command: Write to and Update (Power Up)
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shift_next(15 downto 12) <= "0000"; --Adress: DAC0
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shift_next(11 downto 0) <= val; -- DAC Value (12bit)
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--shift_next(0 downto -3) <= "XXXX"; -- 4x don't care
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when S_WORK => -- currently in work state
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if(counter_reg = 24*2 -1) then
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state_next <= S_IDLE;
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else
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counter_next<= counter_reg + 1;
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end if;
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if(counter_reg(0)='1') then
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shift_next <= shift_left(shift_reg,1);
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end if;
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when others => null; -- do nothing, if we are in a different state
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end case;
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end process NSL;
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end Behavioral;
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