284 lines
8.7 KiB
VHDL
284 lines
8.7 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 18:47:36 05/23/2016
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-- Design Name:
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-- Module Name: controller - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity controller is
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Port ( clk : in STD_LOGIC;
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rst: in STD_LOGIC;
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enc_right : in STD_LOGIC;
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enc_ce : in STD_LOGIC;
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enc_btn: in STD_LOGIC;
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form : in unsigned(1 downto 0);
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lcd_busy: in STD_LOGIC;
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lcd_data: out unsigned(7 downto 0);
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lcd_newchar: out STD_LOGIC;
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lcd_newpos : out STD_LOGIC;
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freq_out : out unsigned (16 downto 0));
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end controller;
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architecture Behavioral of controller is
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type states is(S_WAIT,
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S_FORM_PREF, -- prints the form prefix ("Form:")
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S_FREQ_PREF, -- frequenz prefix ("Freq: 00000 Hz")
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S_FORM_CONT, -- form content ("Rechteck, Sinus...")
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S_FREQ_CONT, -- frequenz content ("-----")
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S_IDLE );
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signal state_reg, state_next : states := S_WAIT;
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signal ret_state_reg, ret_state_next: states := S_FORM_PREF;
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----- Edge detection registers -----
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signal btn_old_reg, btn_old_next : std_logic := '0';
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signal enc_old_reg, enc_old_next: std_logic :='0';
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signal busy_old_reg, busy_old_next : std_logic := '0';
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signal form_old_reg, form_old_next : unsigned (1 downto 0) := (others => '0');
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--digitnr which is currently edited 0-4
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signal digpos_reg, digpos_next : unsigned(2 downto 0) := (others => '0');
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signal charcnt_reg, charcnt_next : unsigned(3 downto 0) := (others => '0');
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-- array 5x 4bit(0-9)
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type storage_digit is array (0 to 7) of unsigned (3 downto 0);
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signal digit_reg, digit_next : storage_digit := (others => (others => '0'));
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signal lcd_newchar_reg,lcd_newchar_next : std_logic := '0';
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signal lcd_newpos_reg,lcd_newpos_next : std_logic := '0';
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signal lcd_data_reg, lcd_data_next: unsigned(7 downto 0) :=(others => '0');
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signal freq_out_reg, freq_out_next : unsigned (16 downto 0) := (others => '0');
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----------------Constants---------------------------------
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type character_array_short is array (0 to 7) of character;
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constant str_form_pref : character_array_short := ( 'F', 'o', 'r','m',':', others => ' ' );
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type character_array_long is array (0 to 15) of character;
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constant str_freq_pref : character_array_long := ( 'F', 'r', 'e','q',':',' ','0','0','0','0','0',' ','H','z', others => ' ' );
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type character_form_array is array (0 to 3, 0 to 7) of character;
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constant str_form : character_form_array := (
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('S','q','u','a','r','e',' ',' '),
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('S','a','w','t','o','o','t','h'),
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('T','r','i','a','n','g','l','e'),
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('S','i','n','e',' ',' ',' ',' ')
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);
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begin
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proc1: process(clk,rst)
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begin
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if(rst='1') then
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digpos_reg <= (others => '0');
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digit_reg <= (others => (others => '0'));
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btn_old_reg <= '0';
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enc_old_reg <='0';
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busy_old_reg <= '0';
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form_old_reg <= "00";
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charcnt_reg <= (others => '0');
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lcd_newchar_reg <= '0';
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lcd_newpos_reg <= '0';
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lcd_data_reg <= (others => '0');
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freq_out_reg <=(others => '0');
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state_reg <= S_WAIT;
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ret_state_reg <= S_FORM_PREF;
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elsif(rising_edge(clk)) then
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digpos_reg <= digpos_next;
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digit_reg <= digit_next;
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btn_old_reg <= btn_old_next;
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enc_old_reg <= enc_old_next;
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busy_old_reg <= busy_old_next;
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form_old_reg <= form_old_next;
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charcnt_reg <= charcnt_next;
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lcd_newchar_reg<= lcd_newchar_next;
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lcd_newpos_reg<= lcd_newpos_next;
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lcd_data_reg <= lcd_data_next;
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freq_out_reg <= freq_out_next;
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state_reg <= state_next;
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ret_state_reg <= ret_state_next;
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end if;
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end process proc1;
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freq_out <= freq_out_reg;
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lcd_data <= lcd_data_reg;
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lcd_newchar <= lcd_newchar_reg;
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lcd_newpos <= lcd_newpos_reg;
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NSL: process(digit_reg,enc_right,enc_ce,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, busy_old_reg, state_reg, ret_state_reg, enc_ce,enc_old_reg, form_old_reg, form)
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begin
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digit_next <= digit_reg;
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digpos_next <= digpos_reg;
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busy_old_next <= lcd_busy;
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btn_old_next <= btn_old_reg;
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enc_old_next <= enc_old_reg;
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form_old_next <= form_old_reg;
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charcnt_next <= charcnt_reg;
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lcd_newchar_next <= '0';
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lcd_newpos_next <= '0';
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lcd_data_next <= lcd_data_reg;
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state_next <= state_reg;
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ret_state_next <= ret_state_reg;
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-- The next statement produces two warnings which can be safely ignored:
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-- xst:643 - The result of a <...>-bit multiplication is partially used...
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freq_out_next <= resize(
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resize(digit_reg(0), 4)
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+ resize(digit_reg(1) ,4)* 10
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+ resize(digit_reg(2) ,7)* 100
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+ resize(digit_reg(3) ,10) * 1000
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+ resize(digit_reg(4) ,14) * 10000
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, 17);
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case state_reg is
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when S_WAIT => -- switch on current state
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if(lcd_busy = '0' and busy_old_reg ='1' ) then
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state_next<= ret_state_reg;
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end if;
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when S_FORM_PREF =>
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state_next <= S_WAIT;
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if(charcnt_reg < 7 ) then
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charcnt_next <= charcnt_reg + 1;
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ret_state_next <= S_FORM_PREF;
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lcd_data_next <= to_unsigned(character'pos(str_form_pref(to_integer(resize(charcnt_reg,3)))),8);
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lcd_newchar_next <= '1';
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else
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charcnt_next <= (others => '0');
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lcd_data_next <= x"40"; --Start adress for line 2
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lcd_newpos_next <= '1';
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ret_state_next <= S_FREQ_PREF;
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end if;
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when S_FREQ_PREF =>
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if(charcnt_reg < 15 ) then
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charcnt_next <= charcnt_reg + 1;
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state_next <= S_WAIT;
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ret_state_next <= S_FREQ_PREF;
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lcd_data_next <= to_unsigned(character'pos(str_freq_pref(to_integer(charcnt_reg))),8);
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lcd_newchar_next <= '1';
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else
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charcnt_next <= (others => '0');
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state_next <= S_FORM_CONT;
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end if;
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when S_FORM_CONT =>
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state_next <= S_WAIT;
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ret_state_next <= S_FORM_CONT;
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charcnt_next <= charcnt_reg + 1;
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if(charcnt_reg < 1 ) then
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lcd_data_next <= x"06"; --adress character 7 on line 1
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lcd_newpos_next <= '1';
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elsif(charcnt_reg < 9) then
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lcd_data_next <= to_unsigned(character'pos(str_form(to_integer(form),to_integer(resize(charcnt_reg-1,3)))),8);
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lcd_newchar_next <= '1';
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else
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charcnt_next <= (others => '0');
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lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
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lcd_newpos_next <= '1';
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ret_state_next <= S_IDLE;
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end if;
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when S_FREQ_CONT =>
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state_next <= S_WAIT;
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if(charcnt_reg < 1 ) then
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charcnt_next <= charcnt_reg + 1;
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ret_state_next <= S_FREQ_CONT;
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lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
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lcd_newpos_next <= '1';
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elsif(charcnt_reg = 1) then
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charcnt_next <= charcnt_reg + 1;
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ret_state_next <= S_FREQ_CONT;
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lcd_data_next <= to_unsigned(character'pos('0'),8) + digit_reg(to_integer(digpos_reg));
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lcd_newchar_next <= '1';
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else
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ret_state_next <= S_IDLE;
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charcnt_next <= (others => '0');
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lcd_data_next <= x"4A" - digpos_reg; -- adress character 11 on line 2 - digit position
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lcd_newpos_next <= '1';
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end if;
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when S_IDLE =>
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btn_old_next <= enc_btn;
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enc_old_next <= enc_ce;
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form_old_next <= form;
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if(form /= form_old_reg) then
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state_next <= S_FORM_CONT;
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elsif(enc_ce='1' and enc_old_reg ='0') then
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if(enc_right='1') then
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if(digit_reg(to_integer(digpos_reg)) = to_unsigned(9,4)) then
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digit_next(to_integer(digpos_reg)) <= to_unsigned(0,4);
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else
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digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) + 1;
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end if;
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else
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if(digit_reg(to_integer(digpos_reg)) = to_unsigned(0,4)) then
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digit_next(to_integer(digpos_reg)) <= to_unsigned(9,4);
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else
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digit_next(to_integer(digpos_reg)) <= digit_reg(to_integer(digpos_reg)) -1;
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end if;
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end if;
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state_next <= S_FREQ_CONT;
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elsif(enc_btn ='1' and btn_old_reg='0') then
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if(digpos_reg = to_unsigned(4,3)) then
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digpos_next <= to_unsigned(0,3);
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else
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digpos_next <= digpos_reg + 1;
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end if;
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state_next <= S_FREQ_CONT;
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end if;
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when others => null; -- do nothing, if we are in a different state
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end case;
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end process NSL;
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end Behavioral;
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