51 lines
1.6 KiB
VHDL
51 lines
1.6 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:29:54 05/09/2016
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-- Design Name:
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-- Module Name: lcddriver - Behavioral
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-- Project Name: yasg
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity lcd_driver is
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Port ( clk : in STD_LOGIC; -- Systemclock (~50MHz)
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data : in STD_LOGIC_VECTOR (7 downto 0); -- either one ascii char (8bit) or new cursor position (0-31)
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new_character : in STD_LOGIC; -- a new character is available on the data bus
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new_pos : in STD_LOGIC; -- a new cursor position is available on the data bus
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auto_incr_cursor : in STD_LOGIC; -- the cursor should automatically be incremented after writing a new character
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lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd databus
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lcd_en : out STD_LOGIC; -- lcd enable
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lcd_rw : out STD_LOGIC; -- lcd read/write
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lcd_rs : out STD_LOGIC); -- lcd register select
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end lcd_driver;
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architecture Behavioral of lcd_driver is
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begin
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end Behavioral;
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