Changed dds to store the whole sin wave in lookup table. works now.
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12
dds.vhd
12
dds.vhd
@@ -28,7 +28,7 @@ entity dds is
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freq_res: natural:=17; -- width of frequency input (log2(max_freq))
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adc_res: natural:=12; -- width of the ouput signal (=adc resolution)
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acc_res: natural:=32; -- width of the phase accumulator
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phase_res: natural:=15); -- effective phase resolution for lookup tables
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phase_res: natural:=10); -- effective phase resolution for sin lookup table
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Port ( clk : in STD_LOGIC;
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freq : in unsigned (freq_res-1 downto 0);
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form : in unsigned (1 downto 0);
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@@ -40,12 +40,15 @@ architecture Behavioral of dds is
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signal idx_phase : unsigned(phase_res-1 downto 0) := (others => '0');
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signal amp_rect, amp_saw, amp_tria, amp_sin : unsigned (adc_res-1 downto 0);
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type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0);
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--type storage is array (((2**phase_res)/4)-1 downto 0) of unsigned (adc_res-2 downto 0);
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type storage is array (((2**phase_res))-1 downto 0) of unsigned (adc_res-1 downto 0);
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function gen_sin_wave return storage is
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variable temp : storage;
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begin
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forLoop: for i in 0 to temp'high loop
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temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1);
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--temp(i) := to_unsigned(integer(real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI/2.0)/real(temp'high))),adc_res-1);
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temp(i) := to_unsigned(integer(real(2**(adc_res-1) -1) + real((2**(adc_res-1))-1)*sin((real(i)*MATH_PI*2.0)/real(temp'high))),adc_res);
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end loop;
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return temp;
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end function gen_sin_wave;
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@@ -72,7 +75,8 @@ begin
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--idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
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idx_phase <= idx(acc_res -1 downto acc_res - phase_res);
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amp_sin <= sin_wave(to_integer(idx_phase));
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-- Modulo is only required to prevent a synthesizer warning, but the value is actually never > 2**phase_res/4
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--amp_sin <= to_unsigned((2**(adc_res-1)) - 1,adc_res) + sin_wave(to_integer(idx_phase) mod ((2**phase_res)/4)) when idx_phase(phase_res-1 downto phase_res-2)="00" else
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