Added generic parameters
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@@ -44,7 +44,8 @@ use ieee.numeric_std.all;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity lcd_driver is
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entity lcd_driver is
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generic ( clk_freq : natural := 50000000; -- frequency of clk (50MHz) in hz
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generic ( NBITS : natural := 16; -- counter bit size
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clk_freq : natural := 50000000; -- frequency of clk (50MHz) in hz
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wait_40000us : natural := 40000; -- wait 40ms
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wait_40000us : natural := 40000; -- wait 40ms
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wait_37us : natural := 37; -- wait 37us
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wait_37us : natural := 37; -- wait 37us
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wait_1520us : natural := 1520); -- wait 1.52ms
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wait_1520us : natural := 1520); -- wait 1.52ms
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@@ -83,10 +84,10 @@ architecture Behavioral of lcd_driver is
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signal ret_state : display_state := INIT; -- ret_state register
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signal ret_state : display_state := INIT; -- ret_state register
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signal next_ret_state : display_state := INIT; -- next_ret_state register
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signal next_ret_state : display_state := INIT; -- next_ret_state register
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signal cur_counter : unsigned(15 downto 0) := (others => '0'); -- 10bit counter signal
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signal cur_counter : unsigned(NBITS-1 downto 0) := (others => '0'); -- 10bit counter signal
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signal next_counter : unsigned(15 downto 0) := (others => '0');
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signal next_counter : unsigned(NBITS-1 downto 0) := (others => '0');
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signal ret_counter : unsigned(15 downto 0) := (others => '0'); -- 10bit counter signal
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signal ret_counter : unsigned(NBITS-1 downto 0) := (others => '0'); -- 10bit counter signal
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signal next_ret_counter : unsigned(15 downto 0) := (others => '0');
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signal next_ret_counter : unsigned(NBITS-1 downto 0) := (others => '0');
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signal next_lcd_db : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); -- next lcd databus
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signal next_lcd_db : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); -- next lcd databus
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signal next_lcd_en : STD_LOGIC := '0'; -- next lcd enable
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signal next_lcd_en : STD_LOGIC := '0'; -- next lcd enable
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@@ -158,7 +159,7 @@ begin
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next_counter <= (others => '0');
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next_counter <= (others => '0');
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next_ret_state <= SEND_FS;
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next_ret_state <= SEND_FS;
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next_ret_counter <= to_unsigned(INIT_COUNT,16);
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next_ret_counter <= to_unsigned(INIT_COUNT,NBITS);
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next_state <= COUNT;
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next_state <= COUNT;
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when SEND_FS =>
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when SEND_FS =>
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@@ -170,7 +171,7 @@ begin
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next_counter <= (others => '0');
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next_counter <= (others => '0');
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next_ret_state <= SEND_SD;
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next_ret_state <= SEND_SD;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,16);
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= COUNT;
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next_state <= COUNT;
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when SEND_SD =>
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when SEND_SD =>
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@@ -182,7 +183,7 @@ begin
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next_counter <= (others => '0');
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next_counter <= (others => '0');
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next_ret_state <= SEND_CD;
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next_ret_state <= SEND_CD;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,16);
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= COUNT;
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next_state <= COUNT;
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when SEND_CD =>
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when SEND_CD =>
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@@ -194,7 +195,7 @@ begin
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next_counter <= (others => '0');
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next_counter <= (others => '0');
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next_ret_state <= PAUSE;
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next_ret_state <= PAUSE;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,16);
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= COUNT;
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next_state <= COUNT;
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when PAUSE =>
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when PAUSE =>
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@@ -206,7 +207,7 @@ begin
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next_counter <= (others => '0');
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next_counter <= (others => '0');
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next_ret_state <= SEND_ES;
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next_ret_state <= SEND_ES;
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next_ret_counter <= to_unsigned(CLEAR_DISPLAY_COUNT,16);
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next_ret_counter <= to_unsigned(CLEAR_DISPLAY_COUNT,NBITS);
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next_state <= COUNT;
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next_state <= COUNT;
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when SEND_ES =>
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when SEND_ES =>
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@@ -218,7 +219,7 @@ begin
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next_counter <= (others => '0');
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next_counter <= (others => '0');
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next_ret_state <= SEND_SA;
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next_ret_state <= SEND_SA;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,16);
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= COUNT;
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next_state <= COUNT;
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when SEND_SA =>
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when SEND_SA =>
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@@ -230,10 +231,11 @@ begin
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next_counter <= (others => '0');
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next_counter <= (others => '0');
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next_ret_state <= DONE;
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next_ret_state <= DONE;
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next_ret_counter <= to_unsigned(PAUSE_COUNT,16);
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next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
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next_state <= COUNT;
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next_state <= COUNT;
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when COUNT =>
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when COUNT =>
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if(cur_counter >= ret_counter) then
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if(cur_counter >= ret_counter) then
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next_state <= ret_state;
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next_state <= ret_state;
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end if;
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end if;
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13
yasg.gise
13
yasg.gise
@@ -57,6 +57,10 @@
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<transform xil_pn:end_ts="1463427125" xil_pn:in_ck="4963174131653437457" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463427125">
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<transform xil_pn:end_ts="1463427125" xil_pn:in_ck="4963174131653437457" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1463427125">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="lcd_driver.vhd"/>
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<outfile xil_pn:name="lcd_driver.vhd"/>
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<outfile xil_pn:name="lcd_driver_tb.vhd"/>
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<outfile xil_pn:name="lcd_driver_tb.vhd"/>
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</transform>
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</transform>
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@@ -75,13 +79,21 @@
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<transform xil_pn:end_ts="1463427127" xil_pn:in_ck="4963174131653437457" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463427127">
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<transform xil_pn:end_ts="1463427127" xil_pn:in_ck="4963174131653437457" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1463427127">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="lcd_driver.vhd"/>
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<outfile xil_pn:name="lcd_driver.vhd"/>
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<outfile xil_pn:name="lcd_driver_tb.vhd"/>
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<outfile xil_pn:name="lcd_driver_tb.vhd"/>
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</transform>
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</transform>
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<transform xil_pn:end_ts="1463427129" xil_pn:in_ck="4963174131653437457" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8378225353365721463" xil_pn:start_ts="1463427127">
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<transform xil_pn:end_ts="1463427129" xil_pn:in_ck="4963174131653437457" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8378225353365721463" xil_pn:start_ts="1463427127">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="fuse.log"/>
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<outfile xil_pn:name="fuse.log"/>
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<outfile xil_pn:name="isim"/>
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<outfile xil_pn:name="isim"/>
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@@ -93,6 +105,7 @@
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<transform xil_pn:end_ts="1463427129" xil_pn:in_ck="-2613076747293757950" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-890565599326071882" xil_pn:start_ts="1463427129">
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<transform xil_pn:end_ts="1463427129" xil_pn:in_ck="-2613076747293757950" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-890565599326071882" xil_pn:start_ts="1463427129">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="OutputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="isim.cmd"/>
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<outfile xil_pn:name="isim.cmd"/>
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