diff --git a/controller.sym b/controller.sym index 758776e..d59c709 100644 --- a/controller.sym +++ b/controller.sym @@ -1,48 +1,45 @@ BLOCK - 2016-6-10T7:49:11 - - - + 2016-6-10T10:10:3 + + - - - - - - - + + + + + + + - - - - - + + + - - + + - - - + + + + + + + + + + + - + + + - - - - - - - - - - diff --git a/controller.vhd b/controller.vhd index 03b2309..4967cfb 100644 --- a/controller.vhd +++ b/controller.vhd @@ -32,10 +32,9 @@ use IEEE.NUMERIC_STD.ALL; entity controller is Port ( clk : in STD_LOGIC; rst: in STD_LOGIC; - enc_updown : in STD_LOGIC; + enc_right : in STD_LOGIC; enc_ce : in STD_LOGIC; enc_btn: in STD_LOGIC; - enc_err : in STD_LOGIC; form : in unsigned(1 downto 0); lcd_busy: in STD_LOGIC; lcd_data: out unsigned(7 downto 0); @@ -144,7 +143,7 @@ begin lcd_newchar <= lcd_newchar_reg; lcd_newpos <= lcd_newpos_reg; - NSL: process(digit_reg,enc_updown,enc_ce,enc_err,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, busy_old_reg, state_reg, ret_state_reg, enc_ce,enc_old_reg, form_old_reg, form) + NSL: process(digit_reg,enc_right,enc_ce,enc_btn,digpos_reg,btn_old_reg, charcnt_reg, lcd_busy, lcd_data_reg, busy_old_reg, state_reg, ret_state_reg, enc_ce,enc_old_reg, form_old_reg, form) begin digit_next <= digit_reg; digpos_next <= digpos_reg; @@ -249,8 +248,8 @@ begin if(form /= form_old_reg) then state_next <= S_FORM_CONT; - elsif(enc_ce='1' and enc_old_reg ='0' and enc_err='0') then - if(enc_updown='1') then + elsif(enc_ce='1' and enc_old_reg ='0') then + if(enc_right='1') then if(digit_reg(to_integer(digpos_reg)) = to_unsigned(9,4)) then digit_next(to_integer(digpos_reg)) <= to_unsigned(0,4); else diff --git a/rotary.vhd b/rotary.vhd index ca11399..b365cb2 100644 --- a/rotary.vhd +++ b/rotary.vhd @@ -11,9 +11,9 @@ entity rotary_dec is Port ( clk : in std_logic; -- Systemtakt A : in std_logic; -- Spur A B : in std_logic; -- Spur B - up_down : out std_logic; -- Zaehlrichtung - ce : out std_logic; -- Clock Enable - error : out std_logic); -- illegaler Signalübergang + right : out std_logic; -- Zaehlrichtung + ce : out std_logic); -- Clock Enable + end rotary_dec; architecture Behavioral of rotary_dec is @@ -41,23 +41,9 @@ variable state: std_logic_vector(3 downto 0); begin state := a_in & b_in & a_old & b_old; case state is - when "0000" => up_down <= '0'; ce <= '0'; error <= '0'; - when "0001" => up_down <= '1'; ce <= '1'; error <= '0'; - when "0010" => up_down <= '0'; ce <= '1'; error <= '0'; - when "0011" => up_down <= '0'; ce <= '0'; error <= '1'; - when "0100" => up_down <= '0'; ce <= '1'; error <= '0'; - when "0101" => up_down <= '0'; ce <= '0'; error <= '0'; - when "0110" => up_down <= '0'; ce <= '0'; error <= '1'; - when "0111" => up_down <= '1'; ce <= '1'; error <= '0'; - when "1000" => up_down <= '1'; ce <= '1'; error <= '0'; - when "1001" => up_down <= '0'; ce <= '0'; error <= '1'; - when "1010" => up_down <= '0'; ce <= '0'; error <= '0'; - when "1011" => up_down <= '0'; ce <= '1'; error <= '0'; - when "1100" => up_down <= '0'; ce <= '0'; error <= '1'; - when "1101" => up_down <= '0'; ce <= '1'; error <= '0'; - when "1110" => up_down <= '1'; ce <= '1'; error <= '0'; - when "1111" => up_down <= '0'; ce <= '0'; error <= '0'; - when others => null; + when "0001" => right <= '0'; ce <= '1'; + when "0010" => right <= '1'; ce <= '1'; + when others => right <= '0'; ce <= '0'; end case; end process; diff --git a/rotary_dec.sym b/rotary_dec.sym index f48b8dc..35a4e5b 100644 --- a/rotary_dec.sym +++ b/rotary_dec.sym @@ -1,13 +1,12 @@ BLOCK - 2016-5-23T16:56:27 + 2016-6-10T10:5:37 - - - + + @@ -17,11 +16,9 @@ - - - - - + + + diff --git a/toplevel.jhd b/toplevel.jhd index c686375..8ac4bfd 100644 --- a/toplevel.jhd +++ b/toplevel.jhd @@ -4,7 +4,7 @@ MODULE toplevel SUBMODULE dds INSTANCE XLXI_2 SUBMODULE controller - INSTANCE XLXI_89 + INSTANCE XLXI_90 SUBMODULE rotary_dec INSTANCE XLXI_43 SUBMODULE lcd_driver diff --git a/toplevel.sch b/toplevel.sch index db11606..b3b0f37 100644 --- a/toplevel.sch +++ b/toplevel.sch @@ -19,9 +19,6 @@ - - - @@ -33,13 +30,14 @@ - + + @@ -50,7 +48,6 @@ - @@ -60,6 +57,7 @@ + 2016-5-20T8:33:2 @@ -106,33 +104,31 @@ - 2016-6-10T7:49:11 - - + 2016-6-10T10:10:3 + - + - + + + + + + + - - - - - - - 2016-5-23T16:56:27 + 2016-6-10T10:5:37 - - + 2016-6-6T19:34:31 @@ -183,9 +179,8 @@ - - - + + @@ -208,20 +203,6 @@ - - - - - - - - - - - - - - @@ -234,6 +215,19 @@ + + + + + + + + + + + + + @@ -268,8 +262,8 @@ - - + + @@ -294,9 +288,6 @@ - - - @@ -306,15 +297,6 @@ - - - - - - - - - @@ -344,7 +326,6 @@ - @@ -352,9 +333,9 @@ - - - + + + @@ -381,17 +362,15 @@ - - - + + + - - + + - - @@ -425,14 +404,11 @@ - + + + - - - - - @@ -441,5 +417,22 @@ + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/yasg.gise b/yasg.gise index 4bf782b..c43b5e3 100644 --- a/yasg.gise +++ b/yasg.gise @@ -237,7 +237,7 @@ - + @@ -262,7 +262,7 @@ - + @@ -289,7 +289,7 @@ - + @@ -298,11 +298,9 @@ - + - - @@ -313,7 +311,7 @@ - + @@ -327,7 +325,7 @@ - + @@ -339,15 +337,13 @@ - + - - - +