diff --git a/lcd_driver.sym b/lcd_driver.sym
index 8fe1742..f3c0d7f 100644
--- a/lcd_driver.sym
+++ b/lcd_driver.sym
@@ -1,15 +1,15 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <symbol version="7" name="lcd_driver">
     <symboltype>BLOCK</symboltype>
-    <timestamp>2016-6-3T14:29:29</timestamp>
+    <timestamp>2016-6-3T16:19:19</timestamp>
     <pin polarity="Input" x="0" y="-352" name="clk" />
     <pin polarity="Input" x="0" y="-288" name="reset" />
     <pin polarity="Input" x="0" y="-224" name="new_character" />
     <pin polarity="Input" x="0" y="-160" name="new_pos" />
     <pin polarity="Input" x="0" y="-96" name="auto_incr_cursor" />
     <pin polarity="Input" x="0" y="-32" name="data(7:0)" />
-    <pin polarity="Output" x="432" y="-352" name="lcd_en" />
-    <pin polarity="Output" x="432" y="-256" name="lcd_rw" />
+    <pin polarity="Output" x="432" y="-352" name="busy" />
+    <pin polarity="Output" x="432" y="-256" name="lcd_en" />
     <pin polarity="Output" x="432" y="-160" name="lcd_rs" />
     <pin polarity="Output" x="432" y="-64" name="lcd_db(7:0)" />
     <graph>
@@ -28,9 +28,9 @@
         <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin data(7:0)" />
         <rect width="64" x="0" y="-44" height="24" />
         <line x2="0" y1="-32" y2="-32" x1="64" />
-        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-352" type="pin lcd_en" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-352" type="pin busy" />
         <line x2="432" y1="-352" y2="-352" x1="368" />
-        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-256" type="pin lcd_rw" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-256" type="pin lcd_en" />
         <line x2="432" y1="-256" y2="-256" x1="368" />
         <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-160" type="pin lcd_rs" />
         <line x2="432" y1="-160" y2="-160" x1="368" />
diff --git a/lcd_driver.vhd b/lcd_driver.vhd
index 9550d3e..4bc2b93 100644
--- a/lcd_driver.vhd
+++ b/lcd_driver.vhd
@@ -215,7 +215,8 @@ begin
                 next_lcd_en <= '1';
                 next_lcd_rs <= '0';
                 
-                if(new_character == '1') then -- send data
+                if(new_character = '1') then -- send data
+						  next_lcd_rs <= '1';
                     next_counter <= (others => '0');
                     next_ret_state <= DONE;
                     next_ret_counter <= to_unsigned(PAUSE_COUNT,NBITS);
@@ -257,6 +258,6 @@ begin
     lcd_db <= cur_lcd_db;
     lcd_en <= cur_lcd_en;
     lcd_rs <= cur_lcd_rs;
-    busy <= '0' when cur_state == DONE else '1';
+    busy <= '0' when cur_state = DONE else '1';
 
 end Behavioral;
\ No newline at end of file
diff --git a/toplevel.sch b/toplevel.sch
index f1df5fc..6883f21 100644
--- a/toplevel.sch
+++ b/toplevel.sch
@@ -33,12 +33,16 @@
         <signal name="XLXN_78" />
         <signal name="XLXN_79" />
         <signal name="XLXN_70" />
-        <signal name="LCD_E" />
-        <signal name="LCD_RW" />
+        <signal name="LCD_busy">
+        </signal>
         <signal name="LCD_RS" />
         <signal name="LCD_DB(7:0)" />
         <signal name="XLXN_92(7:0)" />
         <signal name="XLXN_93" />
+        <signal name="LCD_RW" />
+        <signal name="XLXN_95" />
+        <signal name="XLXN_96" />
+        <signal name="LCD_E" />
         <port polarity="Input" name="CLK_50MHZ" />
         <port polarity="Output" name="SPI_SCK" />
         <port polarity="Output" name="DAC_CS" />
@@ -54,10 +58,10 @@
         <port polarity="Input" name="ROT_A" />
         <port polarity="Input" name="ROT_B" />
         <port polarity="Input" name="ROT_CENTER" />
-        <port polarity="Output" name="LCD_E" />
-        <port polarity="Output" name="LCD_RW" />
         <port polarity="Output" name="LCD_RS" />
         <port polarity="Output" name="LCD_DB(7:0)" />
+        <port polarity="Output" name="LCD_RW" />
+        <port polarity="Output" name="LCD_E" />
         <blockdef name="spi_driver">
             <timestamp>2016-5-20T8:33:2</timestamp>
             <rect width="256" x="64" y="-192" height="192" />
@@ -130,7 +134,7 @@
             <line x2="384" y1="-32" y2="-32" x1="320" />
         </blockdef>
         <blockdef name="lcd_driver">
-            <timestamp>2016-6-3T14:29:29</timestamp>
+            <timestamp>2016-6-3T16:19:19</timestamp>
             <rect width="304" x="64" y="-384" height="384" />
             <line x2="0" y1="-352" y2="-352" x1="64" />
             <line x2="0" y1="-288" y2="-288" x1="64" />
@@ -212,7 +216,7 @@
             <blockpin signalname="CLK_50MHZ" name="clk" />
             <blockpin signalname="XLXN_68" name="rst" />
             <blockpin signalname="XLXN_79" name="enc_err" />
-            <blockpin name="lcd_busy" />
+            <blockpin signalname="LCD_busy" name="lcd_busy" />
             <blockpin signalname="XLXN_93" name="lcd_newchar" />
             <blockpin signalname="FREQ(16:0)" name="freq_out(16:0)" />
             <blockpin signalname="XLXN_77" name="enc_updown" />
@@ -230,11 +234,14 @@
             <blockpin name="new_pos" />
             <blockpin name="auto_incr_cursor" />
             <blockpin signalname="XLXN_92(7:0)" name="data(7:0)" />
+            <blockpin signalname="LCD_busy" name="busy" />
             <blockpin signalname="LCD_E" name="lcd_en" />
-            <blockpin signalname="LCD_RW" name="lcd_rw" />
             <blockpin signalname="LCD_RS" name="lcd_rs" />
             <blockpin signalname="LCD_DB(7:0)" name="lcd_db(7:0)" />
         </block>
+        <block symbolname="gnd" name="XLXI_51">
+            <blockpin signalname="LCD_RW" name="G" />
+        </block>
     </netlist>
     <sheet sheetnum="1" width="5440" height="3520">
         <instance x="2256" y="1520" name="XLXI_2" orien="R0">
@@ -401,12 +408,15 @@
         <branch name="CLK_50MHZ">
             <wire x2="2032" y1="464" y2="464" x1="2000" />
         </branch>
-        <branch name="LCD_E">
+        <branch name="LCD_busy">
+            <attrtext style="alignment:SOFT-BCENTER;fontsize:28;fontname:Arial" attrname="Name" x="960" y="352" type="branch" />
+            <wire x2="96" y1="352" y2="1056" x1="96" />
+            <wire x2="1104" y1="1056" y2="1056" x1="96" />
+            <wire x2="960" y1="352" y2="352" x1="96" />
+            <wire x2="2496" y1="352" y2="352" x1="960" />
+            <wire x2="2496" y1="352" y2="464" x1="2496" />
             <wire x2="2496" y1="464" y2="464" x1="2464" />
         </branch>
-        <branch name="LCD_RW">
-            <wire x2="2496" y1="560" y2="560" x1="2464" />
-        </branch>
         <branch name="LCD_RS">
             <wire x2="2496" y1="656" y2="656" x1="2464" />
         </branch>
@@ -416,8 +426,6 @@
         <instance x="2032" y="816" name="XLXI_45" orien="R0">
         </instance>
         <iomarker fontsize="28" x="2000" y="464" name="CLK_50MHZ" orien="R180" />
-        <iomarker fontsize="28" x="2496" y="464" name="LCD_E" orien="R0" />
-        <iomarker fontsize="28" x="2496" y="560" name="LCD_RW" orien="R0" />
         <iomarker fontsize="28" x="2496" y="656" name="LCD_RS" orien="R0" />
         <iomarker fontsize="28" x="2496" y="752" name="LCD_DB(7:0)" orien="R0" />
         <branch name="XLXN_92(7:0)">
@@ -437,5 +445,16 @@
             <wire x2="1648" y1="416" y2="528" x1="1648" />
             <wire x2="2032" y1="528" y2="528" x1="1648" />
         </branch>
+        <instance x="3088" y="640" name="XLXI_51" orien="R0" />
+        <branch name="LCD_RW">
+            <wire x2="3184" y1="448" y2="448" x1="3152" />
+            <wire x2="3152" y1="448" y2="496" x1="3152" />
+            <wire x2="3152" y1="496" y2="512" x1="3152" />
+        </branch>
+        <iomarker fontsize="28" x="3184" y="448" name="LCD_RW" orien="R0" />
+        <branch name="LCD_E">
+            <wire x2="2496" y1="560" y2="560" x1="2464" />
+        </branch>
+        <iomarker fontsize="28" x="2496" y="560" name="LCD_E" orien="R0" />
     </sheet>
 </drawing>
\ No newline at end of file
diff --git a/yasg.gise b/yasg.gise
index edda31c..f04fd20 100644
--- a/yasg.gise
+++ b/yasg.gise
@@ -73,12 +73,18 @@
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
+    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="lcd_driver.cmd_log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="lcd_driver.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="lcd_driver.ngc"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="lcd_driver.ngr"/>
-    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/>
     <file xil_pn:fileType="FILE_SPL" xil_pn:name="lcd_driver.spl"/>
-    <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/>
     <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="lcd_driver.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="lcd_driver.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="lcd_driver_summary.html"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="lcd_driver_xst.xrpt"/>
     <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="rotary_dec.prj"/>
     <file xil_pn:fileType="FILE_SPL" xil_pn:name="rotary_dec.spl"/>
     <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="rotary_dec.stx"/>
@@ -116,6 +122,7 @@
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="toplevel.prj"/>
     <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="toplevel.ptwx"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="toplevel.stx"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="toplevel.sym" xil_pn:origination="imported"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="toplevel.syr"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="toplevel.twr" xil_pn:subbranch="Par"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="toplevel.twx" xil_pn:subbranch="Par"/>
@@ -183,6 +190,7 @@
     <transform xil_pn:end_ts="1464081246" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1464081246">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForProperties"/>
     </transform>
     <transform xil_pn:end_ts="1464953958" xil_pn:in_ck="7359381923225456452" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1464953958">
       <status xil_pn:value="SuccessfullyRun"/>
@@ -217,7 +225,7 @@
     </transform>
     <transform xil_pn:end_ts="1464954092" xil_pn:in_ck="-1222633688712987584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1464954092">
       <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="NotReadyToRun"/>
+      <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
@@ -229,42 +237,42 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1464964946" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1464964945">
+    <transform xil_pn:end_ts="1464971127" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1464971126">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="toplevel.vhf"/>
     </transform>
-    <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1464958323">
+    <transform xil_pn:end_ts="1464970890" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1464970890">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1464958323">
+    <transform xil_pn:end_ts="1464970890" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1464970890">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2239360189155701135" xil_pn:start_ts="1464958323">
+    <transform xil_pn:end_ts="1464970890" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2239360189155701135" xil_pn:start_ts="1464970890">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1464958323">
+    <transform xil_pn:end_ts="1464970890" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1464970890">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7072966905182239268" xil_pn:start_ts="1464958323">
+    <transform xil_pn:end_ts="1464970890" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7072966905182239268" xil_pn:start_ts="1464970890">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1464964956" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1464964946">
+    <transform xil_pn:end_ts="1464971141" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1464971127">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name=".lso"/>
       <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
+      <outfile xil_pn:name="dds.ngr"/>
       <outfile xil_pn:name="lcd_driver.ngr"/>
+      <outfile xil_pn:name="spi_driver.ngr"/>
       <outfile xil_pn:name="toplevel.jhd"/>
       <outfile xil_pn:name="toplevel.lso"/>
       <outfile xil_pn:name="toplevel.ngc"/>
@@ -277,63 +285,73 @@
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1464964956" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1464964956">
+    <transform xil_pn:end_ts="1464970922" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1464970922">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1464964960" xil_pn:in_ck="4873113828297183477" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1464964956">
+    <transform xil_pn:end_ts="1464971147" xil_pn:in_ck="-2091007341535647977" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1464971141">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="InputRemoved"/>
-      <status xil_pn:value="OutputRemoved"/>
+      <outfile xil_pn:name="_ngo"/>
+      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+      <outfile xil_pn:name="toplevel.bld"/>
+      <outfile xil_pn:name="toplevel.ngd"/>
+      <outfile xil_pn:name="toplevel_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1464964965" xil_pn:in_ck="4873113828297183478" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1464964960">
+    <transform xil_pn:end_ts="1464971153" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1464971147">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="InputRemoved"/>
       <status xil_pn:value="OutputChanged"/>
-      <status xil_pn:value="OutputRemoved"/>
+      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
+      <outfile xil_pn:name="toplevel.pcf"/>
+      <outfile xil_pn:name="toplevel_map.map"/>
+      <outfile xil_pn:name="toplevel_map.mrp"/>
+      <outfile xil_pn:name="toplevel_map.ncd"/>
+      <outfile xil_pn:name="toplevel_map.ngm"/>
+      <outfile xil_pn:name="toplevel_map.xrpt"/>
+      <outfile xil_pn:name="toplevel_summary.xml"/>
+      <outfile xil_pn:name="toplevel_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1464964978" xil_pn:in_ck="2913749866623724303" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1464964965">
+    <transform xil_pn:end_ts="1464971189" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1464971153">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
+      <outfile xil_pn:name="toplevel.ncd"/>
+      <outfile xil_pn:name="toplevel.pad"/>
+      <outfile xil_pn:name="toplevel.par"/>
+      <outfile xil_pn:name="toplevel.ptwx"/>
+      <outfile xil_pn:name="toplevel.unroutes"/>
+      <outfile xil_pn:name="toplevel.xpi"/>
+      <outfile xil_pn:name="toplevel_pad.csv"/>
+      <outfile xil_pn:name="toplevel_pad.txt"/>
+      <outfile xil_pn:name="toplevel_par.xrpt"/>
+    </transform>
+    <transform xil_pn:end_ts="1464971197" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1464971189">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+      <outfile xil_pn:name="toplevel.bgn"/>
+      <outfile xil_pn:name="toplevel.bit"/>
+      <outfile xil_pn:name="toplevel.drc"/>
+      <outfile xil_pn:name="toplevel.ut"/>
+      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
+      <outfile xil_pn:name="webtalk.log"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+    </transform>
+    <transform xil_pn:end_ts="1464971012" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1464971002">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="InputRemoved"/>
-      <status xil_pn:value="OutputRemoved"/>
+      <status xil_pn:value="InputChanged"/>
     </transform>
-    <transform xil_pn:end_ts="1464964985" xil_pn:in_ck="6038244062278944814" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1464964978">
+    <transform xil_pn:end_ts="1464971188" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1464971185">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="InputRemoved"/>
-      <status xil_pn:value="OutputChanged"/>
-      <status xil_pn:value="OutputRemoved"/>
-    </transform>
-    <transform xil_pn:end_ts="1464965048" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1464965047">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-      <status xil_pn:value="InputRemoved"/>
-    </transform>
-    <transform xil_pn:end_ts="1464964978" xil_pn:in_ck="4873113828297183346" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1464964976">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="InputRemoved"/>
-      <status xil_pn:value="OutputRemoved"/>
+      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
+      <outfile xil_pn:name="toplevel.twr"/>
+      <outfile xil_pn:name="toplevel.twx"/>
     </transform>
   </transforms>