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T-moe
2016-06-19 14:18:29 +02:00
parent 295246570f
commit 8a06d7250c
10 changed files with 407 additions and 425 deletions
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32
helpers.vhd
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@@ -1,3 +1,10 @@
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 12:59:01 05/16/2016
----------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
@@ -6,11 +13,9 @@ use IEEE.NUMERIC_STD.ALL;
package helpers is package helpers is
--helper function to calculate the log2 (truncated) of a integer --helper function to calculate the log2 (truncated) of a integer
function log2_int(n:natural) return natural; function log2_int(n:natural) return natural;
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED;
end helpers; end helpers;
package body helpers is package body helpers is
function log2_int(n:natural) return natural is function log2_int(n:natural) return natural is
begin begin
@@ -19,28 +24,5 @@ package body helpers is
end if; end if;
return 1; --since we can no longer divide n, return 1 return 1; --since we can no longer divide n, return 1
end log2_int; end log2_int;
--Source: http://vhdlguru.blogspot.ch/2010/03/vhdl-function-for-division-two-signed.html
function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
variable a1 : unsigned(a'length-1 downto 0):=a;
variable b1 : unsigned(b'length-1 downto 0):=b;
variable p1 : unsigned(b'length downto 0):= (others => '0');
variable i : integer:=0;
begin
for i in 0 to b'length-1 loop
p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
p1(0) := a1(a'length-1);
a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
p1 := p1-b1;
if(p1(b'length-1) ='1') then
a1(0) :='0';
p1 := p1+b1;
else
a1(0) :='1';
end if;
end loop;
return a1;
end divide;
end helpers; end helpers;