Replaced tabs with 3 spaces (ise default)

controller_tb.vhd

@@ -2,7 +2,7 @@
 -- Project:        YASG (Yet another signal generator)
 -- Project Page:   https://github.com/id101010/vhdl-yasg/
 -- Authors:        Aaron Schmocker & Timo Lang
--- License:		    GPL v3
+-- License:        GPL v3
 -- Create Date:    20:08:51 06/06/2016
 --------------------------------------------------------------------------------
 LIBRARY ieee;
@@ -42,7 +42,7 @@ ARCHITECTURE behavior OF controller_tb IS
    signal enc_err : std_logic := '0';
    signal lcd_busy : std_logic := '0';
 
- 	--Outputs
+    --Outputs
    signal lcd_data : unsigned(7 downto 0);
    signal lcd_newchar : std_logic;
    signal freq_out : unsigned(16 downto 0);
@@ -52,7 +52,7 @@ ARCHITECTURE behavior OF controller_tb IS
  
 BEGIN
  
-	-- Instantiate the Unit Under Test (UUT)
+   -- Instantiate the Unit Under Test (UUT)
    uut: controller PORT MAP (
           clk => clk,
           rst => rst,
@@ -69,24 +69,24 @@ BEGIN
    -- Clock process definitions
    clk_process :process
    begin
-		clk <= '0';
-		wait for clk_period/2;
-		clk <= '1';
-		wait for clk_period/2;
+      clk <= '0';
+      wait for clk_period/2;
+      clk <= '1';
+      wait for clk_period/2;
    end process;
  
 
    -- Stimulus process
    stim_proc: process
-   begin		
+   begin      
       -- hold reset state for 100 ns.
-      wait for 100 ns;	
+      wait for 100 ns;   
 
       wait for clk_period*10;
-		
-		rst<= '0';
-		lcd_busy <= '0';
-		
+      
+      rst<= '0';
+      lcd_busy <= '0';
+      
 
       -- insert stimulus here