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Integrated LCD with toplevel, working lcd init.

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This commit is contained in:
id101010
2016-06-03 16:46:04 +02:00
parent 6769253ef3
commit 88b27eb919
6 changed files with 152 additions and 42 deletions
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13
io.ucf
View File

@@ -1,14 +1,12 @@
NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ; NET "CLK_50MHZ" LOC = "E12"| IOSTANDARD = LVCMOS33 ;
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%; NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
NET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "SPI_MOSI" LOC = "AB14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "SPI_SCK" LOC = "AA20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CS" LOC = "W7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "DAC_CS" LOC = "W7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CLR" LOC = "AB13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "DAC_CLR" LOC = "AB13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "DAC_OUT" LOC = "V7" | IOSTANDARD = LVCMOS33 #NET "DAC_OUT" LOC = "V7" | IOSTANDARD = LVCMOS33
NET "J18_IO1" LOC = "AA21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "J18_IO1" LOC = "AA21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "J18_IO2" LOC = "AB21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "J18_IO2" LOC = "AB21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "J18_IO3" LOC = "AA19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "J18_IO3" LOC = "AA19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
@@ -22,3 +20,14 @@ NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP; NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP;
NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN; NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN;
NET "LCD_E" LOC = "AB4" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
NET "LCD_RS" LOC = "Y14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
NET "LCD_RW" LOC = "W13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
NET "LCD_DB<7>" LOC = "Y15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LCD_DB<6>" LOC = "AB16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LCD_DB<5>" LOC = "Y16" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LCD_DB<4>" LOC = "AA12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LCD_DB<3>" LOC = "AB12" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LCD_DB<2>" LOC = "AB17" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LCD_DB<1>" LOC = "AB18" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LCD_DB<0>" LOC = "Y13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

41
lcd_driver.sym Normal file
View File

@@ -0,0 +1,41 @@
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="lcd_driver">
<symboltype>BLOCK</symboltype>
<timestamp>2016-6-3T14:29:29</timestamp>
<pin polarity="Input" x="0" y="-352" name="clk" />
<pin polarity="Input" x="0" y="-288" name="reset" />
<pin polarity="Input" x="0" y="-224" name="new_character" />
<pin polarity="Input" x="0" y="-160" name="new_pos" />
<pin polarity="Input" x="0" y="-96" name="auto_incr_cursor" />
<pin polarity="Input" x="0" y="-32" name="data(7:0)" />
<pin polarity="Output" x="432" y="-352" name="lcd_en" />
<pin polarity="Output" x="432" y="-256" name="lcd_rw" />
<pin polarity="Output" x="432" y="-160" name="lcd_rs" />
<pin polarity="Output" x="432" y="-64" name="lcd_db(7:0)" />
<graph>
<rect width="304" x="64" y="-384" height="384" />
<attrtext style="alignment:BCENTER;fontsize:56;fontname:Arial" attrname="SymbolName" x="216" y="-392" type="symbol" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-352" type="pin clk" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-288" type="pin reset" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-224" type="pin new_character" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-160" type="pin new_pos" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-96" type="pin auto_incr_cursor" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="72" y="-32" type="pin data(7:0)" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-352" type="pin lcd_en" />
<line x2="432" y1="-352" y2="-352" x1="368" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-256" type="pin lcd_rw" />
<line x2="432" y1="-256" y2="-256" x1="368" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-160" type="pin lcd_rs" />
<line x2="432" y1="-160" y2="-160" x1="368" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="360" y="-64" type="pin lcd_db(7:0)" />
<rect width="64" x="368" y="-76" height="24" />
<line x2="432" y1="-64" y2="-64" x1="368" />
</graph>
</symbol>

2
toplevel.jhd
View File

@@ -7,3 +7,5 @@ MODULE toplevel
INSTANCE XLXI_42 INSTANCE XLXI_42
SUBMODULE rotary_dec SUBMODULE rotary_dec
INSTANCE XLXI_43 INSTANCE XLXI_43
SUBMODULE lcd_driver
INSTANCE XLXI_45

71
toplevel.sch
View File

@@ -32,6 +32,11 @@
<signal name="ROT_A" /> <signal name="ROT_A" />
<signal name="ROT_B" /> <signal name="ROT_B" />
<signal name="ROT_CENTER" /> <signal name="ROT_CENTER" />
<signal name="XLXN_70" />
<signal name="LCD_E" />
<signal name="LCD_RW" />
<signal name="LCD_RS" />
<signal name="LCD_DB(7:0)" />
<port polarity="Input" name="CLK_50MHZ" /> <port polarity="Input" name="CLK_50MHZ" />
<port polarity="Output" name="SPI_SCK" /> <port polarity="Output" name="SPI_SCK" />
<port polarity="Output" name="DAC_CS" /> <port polarity="Output" name="DAC_CS" />
@@ -47,6 +52,10 @@
<port polarity="Input" name="ROT_A" /> <port polarity="Input" name="ROT_A" />
<port polarity="Input" name="ROT_B" /> <port polarity="Input" name="ROT_B" />
<port polarity="Input" name="ROT_CENTER" /> <port polarity="Input" name="ROT_CENTER" />
<port polarity="Output" name="LCD_E" />
<port polarity="Output" name="LCD_RW" />
<port polarity="Output" name="LCD_RS" />
<port polarity="Output" name="LCD_DB(7:0)" />
<blockdef name="spi_driver"> <blockdef name="spi_driver">
<timestamp>2016-5-20T8:33:2</timestamp> <timestamp>2016-5-20T8:33:2</timestamp>
<rect width="256" x="64" y="-192" height="192" /> <rect width="256" x="64" y="-192" height="192" />
@@ -114,6 +123,22 @@
<line x2="384" y1="-96" y2="-96" x1="320" /> <line x2="384" y1="-96" y2="-96" x1="320" />
<line x2="384" y1="-32" y2="-32" x1="320" /> <line x2="384" y1="-32" y2="-32" x1="320" />
</blockdef> </blockdef>
<blockdef name="lcd_driver">
<timestamp>2016-6-3T14:29:29</timestamp>
<rect width="304" x="64" y="-384" height="384" />
<line x2="0" y1="-352" y2="-352" x1="64" />
<line x2="0" y1="-288" y2="-288" x1="64" />
<line x2="0" y1="-224" y2="-224" x1="64" />
<line x2="0" y1="-160" y2="-160" x1="64" />
<line x2="0" y1="-96" y2="-96" x1="64" />
<rect width="64" x="0" y="-44" height="24" />
<line x2="0" y1="-32" y2="-32" x1="64" />
<line x2="432" y1="-352" y2="-352" x1="368" />
<line x2="432" y1="-256" y2="-256" x1="368" />
<line x2="432" y1="-160" y2="-160" x1="368" />
<rect width="64" x="368" y="-76" height="24" />
<line x2="432" y1="-64" y2="-64" x1="368" />
</blockdef>
<block symbolname="dds" name="XLXI_2"> <block symbolname="dds" name="XLXI_2">
<blockpin signalname="CLK_50MHZ" name="clk" /> <blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="FREQ(16:0)" name="freq(16:0)" /> <blockpin signalname="FREQ(16:0)" name="freq(16:0)" />
@@ -186,6 +211,21 @@
<block symbolname="gnd" name="XLXI_44"> <block symbolname="gnd" name="XLXI_44">
<blockpin signalname="XLXN_68" name="G" /> <blockpin signalname="XLXN_68" name="G" />
</block> </block>
<block symbolname="lcd_driver" name="XLXI_45">
<blockpin signalname="CLK_50MHZ" name="clk" />
<blockpin signalname="XLXN_70" name="reset" />
<blockpin name="new_character" />
<blockpin name="new_pos" />
<blockpin name="auto_incr_cursor" />
<blockpin name="data(7:0)" />
<blockpin signalname="LCD_E" name="lcd_en" />
<blockpin signalname="LCD_RW" name="lcd_rw" />
<blockpin signalname="LCD_RS" name="lcd_rs" />
<blockpin signalname="LCD_DB(7:0)" name="lcd_db(7:0)" />
</block>
<block symbolname="gnd" name="XLXI_46">
<blockpin signalname="XLXN_70" name="G" />
</block>
</netlist> </netlist>
<sheet sheetnum="1" width="5440" height="3520"> <sheet sheetnum="1" width="5440" height="3520">
<instance x="2256" y="1520" name="XLXI_2" orien="R0"> <instance x="2256" y="1520" name="XLXI_2" orien="R0">
@@ -349,5 +389,36 @@
<wire x2="1232" y1="1216" y2="1216" x1="1200" /> <wire x2="1232" y1="1216" y2="1216" x1="1200" />
</branch> </branch>
<iomarker fontsize="28" x="1200" y="1216" name="ROT_CENTER" orien="R180" /> <iomarker fontsize="28" x="1200" y="1216" name="ROT_CENTER" orien="R180" />
<instance x="1856" y="2176" name="XLXI_45" orien="R0">
</instance>
<branch name="CLK_50MHZ">
<wire x2="1856" y1="1824" y2="1824" x1="1824" />
</branch>
<iomarker fontsize="28" x="1824" y="1824" name="CLK_50MHZ" orien="R180" />
<branch name="XLXN_70">
<wire x2="1696" y1="1888" y2="1920" x1="1696" />
<wire x2="1856" y1="1888" y2="1888" x1="1696" />
</branch>
<instance x="1632" y="2048" name="XLXI_46" orien="R0" />
<branch name="LCD_E">
<wire x2="2304" y1="1824" y2="1824" x1="2288" />
<wire x2="2320" y1="1824" y2="1824" x1="2304" />
</branch>
<branch name="LCD_RW">
<wire x2="2304" y1="1920" y2="1920" x1="2288" />
<wire x2="2320" y1="1920" y2="1920" x1="2304" />
</branch>
<branch name="LCD_RS">
<wire x2="2304" y1="2016" y2="2016" x1="2288" />
<wire x2="2320" y1="2016" y2="2016" x1="2304" />
</branch>
<iomarker fontsize="28" x="2320" y="1824" name="LCD_E" orien="R0" />
<iomarker fontsize="28" x="2320" y="1920" name="LCD_RW" orien="R0" />
<iomarker fontsize="28" x="2320" y="2016" name="LCD_RS" orien="R0" />
<branch name="LCD_DB(7:0)">
<wire x2="2304" y1="2112" y2="2112" x1="2288" />
<wire x2="2320" y1="2112" y2="2112" x1="2304" />
</branch>
<iomarker fontsize="28" x="2320" y="2112" name="LCD_DB(7:0)" orien="R0" />
</sheet> </sheet>
</drawing> </drawing>

57
yasg.gise
View File

@@ -73,8 +73,11 @@
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="lcd_driver.ngr"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="lcd_driver.prj"/>
<file xil_pn:fileType="FILE_SPL" xil_pn:name="lcd_driver.spl"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/> <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="lcd_driver.stx"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="lcd_driver.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/> <file xil_pn:fileType="FILE_XST" xil_pn:name="lcd_driver.xst"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="rotary_dec.prj"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="rotary_dec.prj"/>
<file xil_pn:fileType="FILE_SPL" xil_pn:name="rotary_dec.spl"/> <file xil_pn:fileType="FILE_SPL" xil_pn:name="rotary_dec.spl"/>
@@ -206,8 +209,7 @@
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="dds_tb_beh.prj"/> <status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="dds_tb_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/> <outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/> <outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="isim.log"/>
@@ -215,22 +217,21 @@
</transform> </transform>
<transform xil_pn:end_ts="1464954092" xil_pn:in_ck="-1222633688712987584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1464954092"> <transform xil_pn:end_ts="1464954092" xil_pn:in_ck="-1222633688712987584" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7301171803071747408" xil_pn:start_ts="1464954092">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="dds_tb_isim_beh.wdb"/> <status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
</transform> </transform>
<transform xil_pn:end_ts="1464958322" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1464958322"> <transform xil_pn:end_ts="1464958322" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1464958322">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1464958805" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1464958803"> <transform xil_pn:end_ts="1464964946" xil_pn:in_ck="6038244062278950263" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6927427346963598489" xil_pn:start_ts="1464964945">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<outfile xil_pn:name="toplevel.vhf"/> <outfile xil_pn:name="toplevel.vhf"/>
</transform> </transform>
<transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1464958323"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1929794406770174374" xil_pn:start_ts="1464958323">
@@ -248,24 +249,20 @@
<transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1464958323"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="9102341965431189672" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7072966905182239268" xil_pn:start_ts="1464958323"> <transform xil_pn:end_ts="1464958323" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7072966905182239268" xil_pn:start_ts="1464958323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1464959693" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1464959680"> <transform xil_pn:end_ts="1464964956" xil_pn:in_ck="-5804926608689456155" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="1663716282806445198" xil_pn:start_ts="1464964946">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name=".lso"/> <outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="dds.ngr"/> <outfile xil_pn:name="lcd_driver.ngr"/>
<outfile xil_pn:name="spi_driver.ngr"/>
<outfile xil_pn:name="toplevel.jhd"/> <outfile xil_pn:name="toplevel.jhd"/>
<outfile xil_pn:name="toplevel.lso"/> <outfile xil_pn:name="toplevel.lso"/>
<outfile xil_pn:name="toplevel.ngc"/> <outfile xil_pn:name="toplevel.ngc"/>
@@ -278,27 +275,24 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1464958336" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1464958336"> <transform xil_pn:end_ts="1464964956" xil_pn:in_ck="4242637380" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4784894232377633197" xil_pn:start_ts="1464964956">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1464959698" xil_pn:in_ck="2169537708537049843" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1464959693"> <transform xil_pn:end_ts="1464964960" xil_pn:in_ck="4873113828297183477" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1538882668640856751" xil_pn:start_ts="1464964956">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="toplevel.bld"/> <outfile xil_pn:name="toplevel.bld"/>
<outfile xil_pn:name="toplevel.ngd"/> <outfile xil_pn:name="toplevel.ngd"/>
<outfile xil_pn:name="toplevel_ngdbuild.xrpt"/> <outfile xil_pn:name="toplevel_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1464959705" xil_pn:in_ck="1621356785167787192" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1464959698"> <transform xil_pn:end_ts="1464964965" xil_pn:in_ck="4873113828297183478" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="570889668722473129" xil_pn:start_ts="1464964960">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="toplevel.pcf"/> <outfile xil_pn:name="toplevel.pcf"/>
<outfile xil_pn:name="toplevel_map.map"/> <outfile xil_pn:name="toplevel_map.map"/>
@@ -309,11 +303,9 @@
<outfile xil_pn:name="toplevel_summary.xml"/> <outfile xil_pn:name="toplevel_summary.xml"/>
<outfile xil_pn:name="toplevel_usage.xml"/> <outfile xil_pn:name="toplevel_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1464959723" xil_pn:in_ck="985354266144665770" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1464959705"> <transform xil_pn:end_ts="1464964978" xil_pn:in_ck="2913749866623724303" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-988662182046631445" xil_pn:start_ts="1464964965">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="toplevel.ncd"/> <outfile xil_pn:name="toplevel.ncd"/>
<outfile xil_pn:name="toplevel.pad"/> <outfile xil_pn:name="toplevel.pad"/>
@@ -325,10 +317,11 @@
<outfile xil_pn:name="toplevel_pad.txt"/> <outfile xil_pn:name="toplevel_pad.txt"/>
<outfile xil_pn:name="toplevel_par.xrpt"/> <outfile xil_pn:name="toplevel_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1464959731" xil_pn:in_ck="8640606860472830956" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1464959723"> <transform xil_pn:end_ts="1464964985" xil_pn:in_ck="6038244062278944814" xil_pn:name="TRANEXT_bitFile_spartan3a" xil_pn:prop_ck="-426368325978129584" xil_pn:start_ts="1464964978">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="toplevel.bgn"/> <outfile xil_pn:name="toplevel.bgn"/>
<outfile xil_pn:name="toplevel.bit"/> <outfile xil_pn:name="toplevel.bit"/>
@@ -338,19 +331,13 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1464955208" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1464955207"> <transform xil_pn:end_ts="1464965048" xil_pn:in_ck="6038244062278931960" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5767926783713760761" xil_pn:start_ts="1464965047">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1464959723" xil_pn:in_ck="6034042283462732464" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1464959719"> <transform xil_pn:end_ts="1464964978" xil_pn:in_ck="4873113828297183346" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1464964976">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="toplevel.twr"/> <outfile xil_pn:name="toplevel.twr"/>
<outfile xil_pn:name="toplevel.twx"/> <outfile xil_pn:name="toplevel.twx"/>

8
yasg.xise
View File

@@ -17,11 +17,11 @@
<files> <files>
<file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="lcd_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="dds.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="helpers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
@@ -45,7 +45,7 @@
</file> </file>
<file xil_pn:name="toplevel.sch" xil_pn:type="FILE_SCHEMATIC"> <file xil_pn:name="toplevel.sch" xil_pn:type="FILE_SCHEMATIC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file> </file>
<file xil_pn:name="io.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="io.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -56,7 +56,7 @@
</file> </file>
<file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="lcd_driver_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/>