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Improved port documentation of all modules.

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This commit is contained in:
T-moe
2016-06-19 14:34:41 +02:00
parent 8a06d7250c
commit 78ea176aac
5 changed files with 37 additions and 37 deletions
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22
controller.vhd
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@@ -11,17 +11,17 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity controller is
Port ( clk : in STD_LOGIC;
rst: in STD_LOGIC;
enc_right : in STD_LOGIC;
enc_ce : in STD_LOGIC;
enc_btn: in STD_LOGIC;
form : in unsigned(1 downto 0);
lcd_busy: in STD_LOGIC;
lcd_data: out unsigned(7 downto 0);
lcd_newchar: out STD_LOGIC;
lcd_newpos : out STD_LOGIC;
freq_out : out unsigned (16 downto 0));
Port ( clk : in STD_LOGIC; -- Clock Input
rst: in STD_LOGIC; -- High active, async reset
enc_right : in STD_LOGIC; -- Encoder Input: 1= Direction Right, 0 = Direction Left
enc_ce : in STD_LOGIC; -- Encoder Input: Clock Enable for Signal above
enc_btn: in STD_LOGIC; -- Encoder Input: Debounced Button (High active)
form : in unsigned(1 downto 0); -- Form selection (mapping see dds.vhd)
lcd_busy: in STD_LOGIC; -- LCD Feedback: Busy Signal: 1= LCD is currently busy
lcd_data: out unsigned(7 downto 0); -- LCD Output: Data output
lcd_newchar: out STD_LOGIC; -- LCD Output: Send a new character to the lcd
lcd_newpos : out STD_LOGIC; -- LCD Output: Send a new position/adress to the lcd
freq_out : out unsigned (16 downto 0)); -- Frequency Ouput (Treshould in Hz)
end controller;
architecture Behavioral of controller is

10
dds.vhd
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@@ -13,15 +13,15 @@ use IEEE.MATH_REAL.ALL;
use work.helpers.all;
entity dds is
Generic (clk_freq: natural:= 50000000;
Generic (clk_freq: natural:= 50000000; -- Clock frequency in hz
freq_res: natural:=17; -- width of frequency input (log2(max_freq))
adc_res: natural:=12; -- width of the ouput signal (=adc resolution)
acc_res: natural:=32; -- width of the phase accumulator
phase_res: natural:=10); -- effective phase resolution for sin lookup table
Port ( clk : in STD_LOGIC;
freq : in unsigned (freq_res-1 downto 0);
form : in unsigned (1 downto 0);
amp : out unsigned (adc_res-1 downto 0));
Port ( clk : in STD_LOGIC; -- Clock input
freq : in unsigned (freq_res-1 downto 0); -- Frequenzy input (treshould in Hz)
form : in unsigned (1 downto 0); -- Form selection (00=Rectancle, 01=Sawtooth, 10=Triangle, 11=Sine)
amp : out unsigned (adc_res-1 downto 0)); -- Signal Output (Amplitude)
end dds;
architecture Behavioral of dds is

14
lcd_driver.vhd
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@@ -18,15 +18,15 @@ entity lcd_driver is
wait_between : natural := 37; -- wait 37us
wait_pause : natural := 1520); -- wait 1.52ms
Port ( clk : in STD_LOGIC; -- Systemclock (50MHz)
reset : in STD_LOGIC; -- Initialize display controller
data : in STD_LOGIC_VECTOR (7 downto 0); -- either one ascii char (8bit) or new cursor position (0-31)
Port ( clk : in STD_LOGIC; -- Clock Input
reset : in STD_LOGIC; -- High active, async reset
data : in STD_LOGIC_VECTOR (7 downto 0); -- either one ascii char (8bit) or new cursor position/adress
new_character : in STD_LOGIC; -- a new character is available on the data bus
new_pos : in STD_LOGIC; -- a new cursor position is available on the data bus
busy : out STD_LOGIC; -- 1 when sending stuff
lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd databus
lcd_en : out STD_LOGIC; -- lcd enable
lcd_rs : out STD_LOGIC); -- lcd register select
busy : out STD_LOGIC; -- output which signals that the driver/lcd is currently busy
lcd_db : out STD_LOGIC_VECTOR (7 downto 0); -- lcd output: databus
lcd_en : out STD_LOGIC; -- lcd output: enable
lcd_rs : out STD_LOGIC); -- lcd output: register select
end lcd_driver;
architecture Behavioral of lcd_driver is

12
rotary.vhd
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@@ -11,13 +11,13 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rotary_dec is
Port ( clk : in std_logic; -- Systemtakt
A : in std_logic; -- Spur A
B : in std_logic; -- Spur B
Port ( clk : in std_logic; -- Clock Input
A : in std_logic; -- Signal A
B : in std_logic; -- Signal B
btn : in std_logic; -- Button Input
btn_deb : out std_logic; -- Button entprellt
enc_right: out std_logic; -- Zaehlrichtung
enc_ce : out std_logic); -- Clock Enable
btn_deb : out std_logic; -- Button Output Debonced
enc_right: out std_logic; -- Direction Output: 1=right
enc_ce : out std_logic); -- Clock Enable Output for signal above
end rotary_dec;

16
spi_driver.vhd
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@@ -11,14 +11,14 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_driver is
Generic (clk_freq: natural:= 50000000;
adc_res: natural:=12);
Port ( clk : in STD_LOGIC;
rst: in STD_LOGIC;
val : in unsigned (adc_res-1 downto 0);
sck : out STD_LOGIC;
cs : out STD_LOGIC;
mosi : out STD_LOGIC);
Generic (clk_freq: natural:= 50000000; -- Clock-Frequency in Hz
adc_res: natural:=12); -- Number of bits the DAC has
Port ( clk : in STD_LOGIC; -- Clock input
rst: in STD_LOGIC; -- High active, async reset
val : in unsigned (adc_res-1 downto 0); -- DAC Value to write out
sck : out STD_LOGIC; -- SPI SCK Signal (Clock)
cs : out STD_LOGIC; -- SPI CS Signal (Chip Select)
mosi : out STD_LOGIC); -- SPI MOSI Signal (Master Out Slave in)
end spi_driver;
architecture Behavioral of spi_driver is